Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	426378	0	0
entropy_period_rd_A	2147483647	2095	0	0
intr_enable_rd_A	2147483647	2911	0	0
prefix_0_rd_A	2147483647	2102	0	0
prefix_10_rd_A	2147483647	2180	0	0
prefix_1_rd_A	2147483647	2228	0	0
prefix_2_rd_A	2147483647	2233	0	0
prefix_3_rd_A	2147483647	2196	0	0
prefix_4_rd_A	2147483647	2190	0	0
prefix_5_rd_A	2147483647	2095	0	0
prefix_6_rd_A	2147483647	2178	0	0
prefix_7_rd_A	2147483647	2099	0	0
prefix_8_rd_A	2147483647	2249	0	0
prefix_9_rd_A	2147483647	2213	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	426378	0	0
T26	658358	93515	0	0
T27	134501	0	0	0
T46	0	31264	0	0
T47	0	43556	0	0
T77	0	43819	0	0
T79	0	8657	0	0
T102	0	1	0	0
T108	0	32494	0	0
T109	0	39337	0	0
T110	0	92069	0	0
T111	0	38013	0	0
T113	220065	0	0	0
T114	2926	0	0	0
T115	16094	0	0	0
T116	954144	0	0	0
T117	16569	0	0	0
T118	144704	0	0	0
T119	505180	0	0	0
T120	286940	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2095	0	0
T46	336668	104	0	0
T48	62151	0	0	0
T56	144430	0	0	0
T73	557371	0	0	0
T79	0	28	0	0
T82	0	3	0	0
T103	0	51	0	0
T129	0	3	0	0
T130	0	13	0	0
T131	0	23	0	0
T132	0	126	0	0
T133	0	12	0	0
T134	0	2	0	0
T135	124468	0	0	0
T136	65387	0	0	0
T137	7768	0	0	0
T138	177365	0	0	0
T139	1940	0	0	0
T140	1268	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2911	0	0
T46	336668	72	0	0
T48	62151	0	0	0
T56	144430	0	0	0
T73	557371	0	0	0
T79	0	25	0	0
T106	0	10	0	0
T107	0	13	0	0
T129	0	2	0	0
T130	0	20	0	0
T131	0	12	0	0
T132	0	240	0	0
T133	0	23	0	0
T135	124468	0	0	0
T136	65387	0	0	0
T137	7768	0	0	0
T138	177365	0	0	0
T139	1940	0	0	0
T140	1268	0	0	0
T141	0	12	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2102	0	0
T46	336668	57	0	0
T48	62151	0	0	0
T56	144430	0	0	0
T73	557371	0	0	0
T79	0	30	0	0
T82	0	5	0	0
T103	0	33	0	0
T129	0	1	0	0
T130	0	4	0	0
T131	0	20	0	0
T132	0	198	0	0
T133	0	9	0	0
T134	0	2	0	0
T135	124468	0	0	0
T136	65387	0	0	0
T137	7768	0	0	0
T138	177365	0	0	0
T139	1940	0	0	0
T140	1268	0	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2180	0	0
T46	336668	46	0	0
T48	62151	0	0	0
T56	144430	0	0	0
T73	557371	0	0	0
T79	0	17	0	0
T82	0	4	0	0
T83	0	52	0	0
T103	0	43	0	0
T129	0	3	0	0
T130	0	5	0	0
T131	0	21	0	0
T132	0	237	0	0
T133	0	30	0	0
T135	124468	0	0	0
T136	65387	0	0	0
T137	7768	0	0	0
T138	177365	0	0	0
T139	1940	0	0	0
T140	1268	0	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2228	0	0
T46	336668	78	0	0
T48	62151	0	0	0
T56	144430	0	0	0
T73	557371	0	0	0
T79	0	30	0	0
T82	0	4	0	0
T83	0	69	0	0
T103	0	32	0	0
T130	0	6	0	0
T131	0	11	0	0
T132	0	208	0	0
T133	0	38	0	0
T134	0	9	0	0
T135	124468	0	0	0
T136	65387	0	0	0
T137	7768	0	0	0
T138	177365	0	0	0
T139	1940	0	0	0
T140	1268	0	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2233	0	0
T46	336668	74	0	0
T48	62151	0	0	0
T56	144430	0	0	0
T73	557371	0	0	0
T79	0	30	0	0
T103	0	37	0	0
T129	0	3	0	0
T130	0	9	0	0
T131	0	17	0	0
T132	0	247	0	0
T133	0	44	0	0
T134	0	4	0	0
T135	124468	0	0	0
T136	65387	0	0	0
T137	7768	0	0	0
T138	177365	0	0	0
T139	1940	0	0	0
T140	1268	0	0	0
T142	0	4	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2196	0	0
T46	336668	94	0	0
T48	62151	0	0	0
T56	144430	0	0	0
T73	557371	0	0	0
T79	0	29	0	0
T82	0	6	0	0
T83	0	49	0	0
T103	0	38	0	0
T129	0	13	0	0
T130	0	9	0	0
T131	0	14	0	0
T132	0	210	0	0
T133	0	38	0	0
T135	124468	0	0	0
T136	65387	0	0	0
T137	7768	0	0	0
T138	177365	0	0	0
T139	1940	0	0	0
T140	1268	0	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2190	0	0
T46	336668	95	0	0
T48	62151	0	0	0
T56	144430	0	0	0
T73	557371	0	0	0
T79	0	37	0	0
T82	0	12	0	0
T103	0	48	0	0
T129	0	8	0	0
T130	0	2	0	0
T131	0	11	0	0
T132	0	244	0	0
T133	0	28	0	0
T135	124468	0	0	0
T136	65387	0	0	0
T137	7768	0	0	0
T138	177365	0	0	0
T139	1940	0	0	0
T140	1268	0	0	0
T142	0	3	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2095	0	0
T46	336668	76	0	0
T48	62151	0	0	0
T56	144430	0	0	0
T73	557371	0	0	0
T79	0	12	0	0
T82	0	10	0	0
T103	0	31	0	0
T129	0	11	0	0
T130	0	3	0	0
T131	0	17	0	0
T132	0	232	0	0
T133	0	3	0	0
T134	0	4	0	0
T135	124468	0	0	0
T136	65387	0	0	0
T137	7768	0	0	0
T138	177365	0	0	0
T139	1940	0	0	0
T140	1268	0	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2178	0	0
T46	336668	58	0	0
T48	62151	0	0	0
T56	144430	0	0	0
T73	557371	0	0	0
T79	0	33	0	0
T82	0	1	0	0
T103	0	62	0	0
T129	0	3	0	0
T130	0	4	0	0
T131	0	20	0	0
T132	0	229	0	0
T133	0	18	0	0
T134	0	3	0	0
T135	124468	0	0	0
T136	65387	0	0	0
T137	7768	0	0	0
T138	177365	0	0	0
T139	1940	0	0	0
T140	1268	0	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2099	0	0
T46	336668	71	0	0
T48	62151	0	0	0
T56	144430	0	0	0
T73	557371	0	0	0
T79	0	26	0	0
T82	0	6	0	0
T83	0	54	0	0
T103	0	34	0	0
T129	0	1	0	0
T130	0	6	0	0
T131	0	22	0	0
T132	0	224	0	0
T134	0	2	0	0
T135	124468	0	0	0
T136	65387	0	0	0
T137	7768	0	0	0
T138	177365	0	0	0
T139	1940	0	0	0
T140	1268	0	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2249	0	0
T46	336668	104	0	0
T48	62151	0	0	0
T56	144430	0	0	0
T73	557371	0	0	0
T79	0	20	0	0
T82	0	6	0	0
T103	0	44	0	0
T129	0	5	0	0
T130	0	6	0	0
T131	0	26	0	0
T132	0	249	0	0
T133	0	40	0	0
T134	0	4	0	0
T135	124468	0	0	0
T136	65387	0	0	0
T137	7768	0	0	0
T138	177365	0	0	0
T139	1940	0	0	0
T140	1268	0	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2213	0	0
T46	336668	91	0	0
T48	62151	0	0	0
T56	144430	0	0	0
T73	557371	0	0	0
T79	0	19	0	0
T103	0	59	0	0
T112	0	9	0	0
T130	0	2	0	0
T131	0	23	0	0
T132	0	243	0	0
T133	0	18	0	0
T134	0	5	0	0
T135	124468	0	0	0
T136	65387	0	0	0
T137	7768	0	0	0
T138	177365	0	0	0
T139	1940	0	0	0
T140	1268	0	0	0
T143	0	6	0	0