Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	253110092	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

199737709

1

T1

161

T2

100207

T3

166

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	239166308	1			T1	74		T2	125751		T3	90
values[0x0]	102656653	1			T1	52		T2	545524		T3	50
values[0x1]	111024840	1			T1	46		T2	588055		T3	42

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	197283439	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

255564362

1

T1

165

T2

130459

T3

171

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1367382	1			T2	9225		T9	1804		T14	11
valid_sources[0x01]	1364936	1			T2	9358		T9	1796		T14	19
valid_sources[0x02]	2013603	1			T2	9236		T3	1		T9	1725
valid_sources[0x03]	1363689	1			T2	9026		T3	5		T9	1791
valid_sources[0x04]	1364819	1			T1	4		T2	9463		T9	1788
valid_sources[0x05]	2042645	1			T2	9220		T9	1800		T13	36
valid_sources[0x06]	1372068	1			T1	10		T2	9360		T9	1776
valid_sources[0x07]	1402326	1			T2	9355		T9	1859		T14	13
valid_sources[0x08]	1358938	1			T2	9218		T9	1760		T14	11
valid_sources[0x09]	2463488	1			T2	9391		T9	1899		T14	12
valid_sources[0x0a]	1362201	1			T2	9171		T9	1749		T14	7
valid_sources[0x0b]	1413455	1			T2	9152		T9	1835		T14	6
valid_sources[0x0c]	1649420	1			T2	9205		T9	1756		T14	11
valid_sources[0x0d]	1457844	1			T2	9453		T9	1734		T14	18
valid_sources[0x0e]	1447819	1			T2	9580		T9	1736		T13	32
valid_sources[0x0f]	1819636	1			T1	17		T2	9809		T9	1816
valid_sources[0x10]	1436072	1			T2	9439		T9	1779		T14	10
valid_sources[0x11]	1598929	1			T1	4		T2	9218		T9	1828
valid_sources[0x12]	1369792	1			T2	9621		T9	1826		T13	25
valid_sources[0x13]	1358891	1			T2	9595		T3	1		T9	1797
valid_sources[0x14]	1708960	1			T2	9336		T9	1808		T14	16
valid_sources[0x15]	1367033	1			T2	9504		T3	3		T9	1772
valid_sources[0x16]	2036093	1			T2	9519		T9	1858		T13	54
valid_sources[0x17]	1361744	1			T2	9350		T9	1810		T14	15
valid_sources[0x18]	1370857	1			T2	9223		T9	1838		T13	46
valid_sources[0x19]	1427957	1			T2	9653		T9	1802		T14	25
valid_sources[0x1a]	1491335	1			T2	9365		T9	1754		T14	15
valid_sources[0x1b]	1376444	1			T2	9071		T3	4		T9	1719
valid_sources[0x1c]	1375516	1			T2	9356		T9	1678		T13	60
valid_sources[0x1d]	1450069	1			T2	9478		T3	2		T9	1734
valid_sources[0x1e]	1364339	1			T1	5		T2	9160		T9	1804
valid_sources[0x1f]	1364708	1			T2	9201		T9	1842		T14	14
valid_sources[0x20]	1366910	1			T2	9448		T9	1847		T14	16
valid_sources[0x21]	2699234	1			T2	8959		T9	1731		T14	10
valid_sources[0x22]	1368764	1			T2	9152		T9	1743		T13	7
valid_sources[0x23]	1364124	1			T2	9323		T9	1771		T13	16
valid_sources[0x24]	1365549	1			T2	9391		T9	1757		T14	11
valid_sources[0x25]	3826979	1			T2	9106		T9	1754		T14	10
valid_sources[0x26]	1368052	1			T2	9704		T9	1652		T14	13
valid_sources[0x27]	1358543	1			T2	9431		T9	1771		T14	12
valid_sources[0x28]	1359489	1			T2	9421		T9	1835		T13	37
valid_sources[0x29]	4357245	1			T2	9300		T9	1767		T14	12
valid_sources[0x2a]	1365839	1			T2	9277		T9	1758		T14	12
valid_sources[0x2b]	2225552	1			T2	9085		T3	3		T9	1716
valid_sources[0x2c]	1367664	1			T1	2		T2	9131		T3	1
valid_sources[0x2d]	1453514	1			T2	9466		T3	4		T9	1795
valid_sources[0x2e]	1681698	1			T1	4		T2	9269		T9	1766
valid_sources[0x2f]	1475345	1			T2	9593		T9	1778		T14	8
valid_sources[0x30]	1688614	1			T2	9267		T9	1790		T14	14
valid_sources[0x31]	1369753	1			T2	9137		T3	3		T9	1745
valid_sources[0x32]	1366656	1			T2	9283		T3	1		T9	1700
valid_sources[0x33]	2233240	1			T2	9177		T9	1752		T14	12
valid_sources[0x34]	1363736	1			T2	9712		T9	1794		T14	12
valid_sources[0x35]	3800736	1			T2	9402		T3	3		T9	1807
valid_sources[0x36]	4249099	1			T2	9237		T9	1772		T14	10
valid_sources[0x37]	1371807	1			T1	3		T2	9351		T3	1
valid_sources[0x38]	1487717	1			T2	9616		T3	3		T9	1772
valid_sources[0x39]	1375471	1			T2	9202		T3	4		T9	1735
valid_sources[0x3a]	1362488	1			T2	9200		T3	2		T9	1812
valid_sources[0x3b]	1392037	1			T2	9334		T9	1761		T14	12
valid_sources[0x3c]	1358909	1			T2	9354		T3	9		T9	1852
valid_sources[0x3d]	1824706	1			T2	9636		T9	1734		T14	10
valid_sources[0x3e]	1480367	1			T2	9492		T9	1853		T14	9
valid_sources[0x3f]	1362818	1			T2	9436		T9	1797		T13	67
valid_sources[0x40]	1368074	1			T2	9545		T9	1770		T14	5
valid_sources[0x41]	1362004	1			T1	8		T2	9385		T9	1836
valid_sources[0x42]	2033578	1			T2	8906		T9	1779		T13	25
valid_sources[0x43]	1588633	1			T2	9238		T9	1745		T14	11
valid_sources[0x44]	1380318	1			T2	8946		T9	1823		T14	13
valid_sources[0x45]	1371202	1			T2	9328		T9	1882		T13	11
valid_sources[0x46]	1368342	1			T2	9518		T3	6		T9	1795
valid_sources[0x47]	1362782	1			T2	9265		T9	1729		T13	58
valid_sources[0x48]	1369150	1			T2	9308		T9	1803		T14	7
valid_sources[0x49]	1365130	1			T2	9586		T9	1710		T14	12
valid_sources[0x4a]	2040409	1			T2	9028		T9	1792		T13	18
valid_sources[0x4b]	2586943	1			T2	9346		T3	3		T9	1718
valid_sources[0x4c]	1365791	1			T2	9390		T9	1743		T14	11
valid_sources[0x4d]	1366491	1			T2	9348		T9	1821		T14	18
valid_sources[0x4e]	1365616	1			T1	2		T2	9053		T9	1773
valid_sources[0x4f]	1367809	1			T2	9172		T3	5		T9	1701
valid_sources[0x50]	1363885	1			T2	9385		T3	3		T9	1810
valid_sources[0x51]	1482537	1			T2	9764		T9	1715		T14	10
valid_sources[0x52]	3818745	1			T2	9520		T9	1791		T14	14
valid_sources[0x53]	1489724	1			T1	2		T2	8955		T9	1786
valid_sources[0x54]	1383495	1			T2	9554		T9	1747		T13	37
valid_sources[0x55]	1364668	1			T2	9097		T9	1769		T14	15
valid_sources[0x56]	1366251	1			T2	9235		T3	7		T9	1677
valid_sources[0x57]	1723356	1			T2	9119		T9	1798		T14	11
valid_sources[0x58]	1477299	1			T2	9830		T3	3		T9	1810
valid_sources[0x59]	3435718	1			T2	9064		T9	1814		T14	19
valid_sources[0x5a]	2201039	1			T1	11		T2	9008		T9	1708
valid_sources[0x5b]	2266927	1			T2	9408		T9	1801		T13	18
valid_sources[0x5c]	1421589	1			T2	9118		T9	1764		T14	17
valid_sources[0x5d]	1369668	1			T2	9202		T9	1795		T13	4
valid_sources[0x5e]	3766616	1			T2	9265		T3	1		T9	1760
valid_sources[0x5f]	4234793	1			T2	9598		T9	1776		T14	13
valid_sources[0x60]	1363792	1			T2	9476		T9	1746		T13	10
valid_sources[0x61]	1369201	1			T2	9511		T9	1787		T14	16
valid_sources[0x62]	2046713	1			T1	4		T2	9413		T9	1799
valid_sources[0x63]	1364927	1			T2	9433		T3	3		T9	1771
valid_sources[0x64]	1532720	1			T2	9355		T9	1857		T13	21
valid_sources[0x65]	4582328	1			T2	9141		T9	1792		T14	17
valid_sources[0x66]	1367453	1			T2	9428		T9	1748		T14	12
valid_sources[0x67]	1360229	1			T2	9547		T9	1739		T14	10
valid_sources[0x68]	1366611	1			T2	9324		T9	1732		T14	8
valid_sources[0x69]	1361786	1			T2	9405		T9	1773		T14	11
valid_sources[0x6a]	1389235	1			T2	9208		T9	1809		T13	2
valid_sources[0x6b]	1364167	1			T1	7		T2	9490		T9	1760
valid_sources[0x6c]	1425892	1			T2	9219		T9	1746		T13	58
valid_sources[0x6d]	1367037	1			T2	9710		T9	1788		T13	9
valid_sources[0x6e]	3762795	1			T2	9274		T9	1745		T14	15
valid_sources[0x6f]	1594130	1			T1	5		T2	9229		T9	1810
valid_sources[0x70]	1361449	1			T2	9487		T9	1805		T14	9
valid_sources[0x71]	3374019	1			T2	9242		T3	7		T9	1803
valid_sources[0x72]	2470025	1			T2	9282		T3	2		T9	1771
valid_sources[0x73]	1820280	1			T2	9231		T9	1810		T14	11
valid_sources[0x74]	1378686	1			T2	9587		T9	1802		T14	15
valid_sources[0x75]	1366043	1			T2	9102		T9	1755		T13	6
valid_sources[0x76]	2241305	1			T2	9147		T3	3		T9	1793
valid_sources[0x77]	1366536	1			T2	9186		T3	1		T9	1791
valid_sources[0x78]	1389418	1			T2	9240		T3	1		T9	1842
valid_sources[0x79]	1832652	1			T2	9061		T9	1757		T14	7
valid_sources[0x7a]	1367974	1			T2	9432		T9	1701		T14	19
valid_sources[0x7b]	1364788	1			T1	1		T2	9432		T9	1767
valid_sources[0x7c]	2271418	1			T2	9182		T4	2070		T9	1675
valid_sources[0x7d]	1369464	1			T2	9259		T9	1791		T14	11
valid_sources[0x7e]	1365889	1			T2	9176		T3	1		T9	1782
valid_sources[0x7f]	1816221	1			T2	9485		T9	1709		T13	24
valid_sources[0x80]	1366518	1			T2	9130		T3	3		T9	1796

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

87317553

1

T1

72

T2

422750

T3

85

values[0x0]

all_enables

biggest_size

60482740

1

T1

47

T2

313500

T3

45

values[0x1]

all_enables

biggest_size

51937416

1

T1

42

T2

265828

T3

36