Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

256092212

1

T1

11

T2

138901

T3

16

full_word

199924869

1

T1

161

T2

100207

T3

166

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	456016771	1			T1	172		T2	239109		T3	182
auto[TlIntgErrCmd]	105	1			T117	7		T118	10		T119	5
auto[TlIntgErrData]	100	1			T117	7		T118	4		T119	6
auto[TlIntgErrBoth]	105	1			T117	6		T118	6		T119	9

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

239742578

1

T1

74

T2

125751

T3

90

auto[1]

216274503

1

T1

98

T2

113357

T3

92

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	152377985	1			T1	2		T2	834768		T3	5
auto[TlIntgErrNone]	partial	auto[1]	103713946	1			T1	9		T2	554251		T3	11
auto[TlIntgErrNone]	full_word	auto[0]	87364445	1			T1	72		T2	422750		T3	85
auto[TlIntgErrNone]	full_word	auto[1]	112560395	1			T1	89		T2	579328		T3	81
auto[TlIntgErrCmd]	partial	auto[0]	46	1			T117	1		T118	5		T119	2
auto[TlIntgErrCmd]	partial	auto[1]	51	1			T117	4		T118	4		T119	1
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T118	1		T184	1		T185	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T117	2		T119	2		T185	1
auto[TlIntgErrData]	partial	auto[0]	44	1			T117	2		T118	2		T119	4
auto[TlIntgErrData]	partial	auto[1]	44	1			T117	3		T118	1		T119	1
auto[TlIntgErrData]	full_word	auto[0]	6	1			T117	1		T183	1		T186	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T117	1		T118	1		T119	1
auto[TlIntgErrBoth]	partial	auto[0]	44	1			T117	3		T118	3		T119	3
auto[TlIntgErrBoth]	partial	auto[1]	52	1			T117	3		T118	3		T119	5
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T187	1		T183	1		T186	3
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T119	1		T188	1		T189	1