Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	695445	0	0
entropy_period_rd_A	2147483647	1869	0	0
intr_enable_rd_A	2147483647	2161	0	0
prefix_0_rd_A	2147483647	1592	0	0
prefix_10_rd_A	2147483647	1654	0	0
prefix_1_rd_A	2147483647	1639	0	0
prefix_2_rd_A	2147483647	1628	0	0
prefix_3_rd_A	2147483647	1582	0	0
prefix_4_rd_A	2147483647	1646	0	0
prefix_5_rd_A	2147483647	1667	0	0
prefix_6_rd_A	2147483647	1750	0	0
prefix_7_rd_A	2147483647	1579	0	0
prefix_8_rd_A	2147483647	1616	0	0
prefix_9_rd_A	2147483647	1662	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	695445	0	0
T18	805428	78230	0	0
T19	612252	0	0	0
T27	141749	0	0	0
T30	948889	0	0	0
T34	0	171376	0	0
T41	189332	0	0	0
T42	333890	0	0	0
T43	473175	0	0	0
T44	66899	0	0	0
T45	20915	0	0	0
T46	204817	0	0	0
T59	0	20095	0	0
T96	0	42120	0	0
T97	0	11256	0	0
T123	0	24098	0	0
T124	0	35986	0	0
T125	0	34551	0	0
T126	0	193141	0	0
T127	0	59721	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1869	0	0
T97	137090	38	0	0
T104	0	59	0	0
T110	0	4	0	0
T113	0	14	0	0
T119	0	48	0	0
T140	0	220	0	0
T141	0	4	0	0
T142	0	18	0	0
T143	0	11	0	0
T144	0	5	0	0
T145	16169	0	0	0
T146	130473	0	0	0
T147	943954	0	0	0
T148	431819	0	0	0
T149	3729	0	0	0
T150	222622	0	0	0
T151	385692	0	0	0
T152	186280	0	0	0
T153	315888	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2161	0	0
T97	137090	26	0	0
T104	0	82	0	0
T140	0	188	0	0
T141	0	8	0	0
T142	0	11	0	0
T145	16169	0	0	0
T146	130473	0	0	0
T147	943954	0	0	0
T148	431819	0	0	0
T149	3729	0	0	0
T150	222622	0	0	0
T151	385692	0	0	0
T152	186280	0	0	0
T153	315888	0	0	0
T154	0	4	0	0
T155	0	13	0	0
T156	0	31	0	0
T157	0	2	0	0
T158	0	10	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1592	0	0
T97	137090	51	0	0
T104	0	57	0	0
T106	0	26	0	0
T113	0	10	0	0
T119	0	29	0	0
T140	0	238	0	0
T141	0	5	0	0
T142	0	9	0	0
T144	0	3	0	0
T145	16169	0	0	0
T146	130473	0	0	0
T147	943954	0	0	0
T148	431819	0	0	0
T149	3729	0	0	0
T150	222622	0	0	0
T151	385692	0	0	0
T152	186280	0	0	0
T153	315888	0	0	0
T159	0	4	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1654	0	0
T97	137090	70	0	0
T104	0	54	0	0
T106	0	10	0	0
T113	0	13	0	0
T119	0	42	0	0
T140	0	218	0	0
T142	0	11	0	0
T144	0	5	0	0
T145	16169	0	0	0
T146	130473	0	0	0
T147	943954	0	0	0
T148	431819	0	0	0
T149	3729	0	0	0
T150	222622	0	0	0
T151	385692	0	0	0
T152	186280	0	0	0
T153	315888	0	0	0
T159	0	9	0	0
T160	0	13	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1639	0	0
T97	137090	42	0	0
T104	0	56	0	0
T106	0	27	0	0
T113	0	21	0	0
T119	0	16	0	0
T140	0	218	0	0
T141	0	7	0	0
T142	0	8	0	0
T144	0	3	0	0
T145	16169	0	0	0
T146	130473	0	0	0
T147	943954	0	0	0
T148	431819	0	0	0
T149	3729	0	0	0
T150	222622	0	0	0
T151	385692	0	0	0
T152	186280	0	0	0
T153	315888	0	0	0
T159	0	1	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1628	0	0
T97	137090	49	0	0
T104	0	51	0	0
T110	0	2	0	0
T113	0	14	0	0
T140	0	187	0	0
T141	0	5	0	0
T142	0	11	0	0
T143	0	7	0	0
T144	0	2	0	0
T145	16169	0	0	0
T146	130473	0	0	0
T147	943954	0	0	0
T148	431819	0	0	0
T149	3729	0	0	0
T150	222622	0	0	0
T151	385692	0	0	0
T152	186280	0	0	0
T153	315888	0	0	0
T161	0	3	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1582	0	0
T97	137090	61	0	0
T104	0	52	0	0
T113	0	20	0	0
T119	0	35	0	0
T140	0	171	0	0
T142	0	15	0	0
T143	0	2	0	0
T144	0	5	0	0
T145	16169	0	0	0
T146	130473	0	0	0
T147	943954	0	0	0
T148	431819	0	0	0
T149	3729	0	0	0
T150	222622	0	0	0
T151	385692	0	0	0
T152	186280	0	0	0
T153	315888	0	0	0
T159	0	4	0	0
T161	0	12	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1646	0	0
T97	137090	57	0	0
T104	0	64	0	0
T106	0	20	0	0
T113	0	17	0	0
T119	0	48	0	0
T140	0	222	0	0
T142	0	12	0	0
T143	0	11	0	0
T144	0	2	0	0
T145	16169	0	0	0
T146	130473	0	0	0
T147	943954	0	0	0
T148	431819	0	0	0
T149	3729	0	0	0
T150	222622	0	0	0
T151	385692	0	0	0
T152	186280	0	0	0
T153	315888	0	0	0
T160	0	17	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1667	0	0
T97	137090	69	0	0
T104	0	38	0	0
T113	0	17	0	0
T119	0	32	0	0
T140	0	198	0	0
T141	0	4	0	0
T142	0	7	0	0
T143	0	6	0	0
T144	0	8	0	0
T145	16169	0	0	0
T146	130473	0	0	0
T147	943954	0	0	0
T148	431819	0	0	0
T149	3729	0	0	0
T150	222622	0	0	0
T151	385692	0	0	0
T152	186280	0	0	0
T153	315888	0	0	0
T161	0	9	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1750	0	0
T97	137090	37	0	0
T104	0	71	0	0
T113	0	11	0	0
T119	0	59	0	0
T140	0	210	0	0
T141	0	8	0	0
T142	0	7	0	0
T143	0	1	0	0
T144	0	7	0	0
T145	16169	0	0	0
T146	130473	0	0	0
T147	943954	0	0	0
T148	431819	0	0	0
T149	3729	0	0	0
T150	222622	0	0	0
T151	385692	0	0	0
T152	186280	0	0	0
T153	315888	0	0	0
T161	0	1	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1579	0	0
T97	137090	28	0	0
T104	0	57	0	0
T113	0	22	0	0
T119	0	35	0	0
T140	0	226	0	0
T141	0	5	0	0
T142	0	1	0	0
T143	0	2	0	0
T144	0	7	0	0
T145	16169	0	0	0
T146	130473	0	0	0
T147	943954	0	0	0
T148	431819	0	0	0
T149	3729	0	0	0
T150	222622	0	0	0
T151	385692	0	0	0
T152	186280	0	0	0
T153	315888	0	0	0
T161	0	7	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1616	0	0
T97	137090	30	0	0
T104	0	56	0	0
T113	0	16	0	0
T119	0	49	0	0
T140	0	206	0	0
T141	0	7	0	0
T142	0	9	0	0
T145	16169	0	0	0
T146	130473	0	0	0
T147	943954	0	0	0
T148	431819	0	0	0
T149	3729	0	0	0
T150	222622	0	0	0
T151	385692	0	0	0
T152	186280	0	0	0
T153	315888	0	0	0
T159	0	3	0	0
T161	0	14	0	0
T162	0	3	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1662	0	0
T97	137090	72	0	0
T104	0	65	0	0
T113	0	13	0	0
T119	0	66	0	0
T140	0	189	0	0
T141	0	6	0	0
T142	0	12	0	0
T143	0	7	0	0
T144	0	4	0	0
T145	16169	0	0	0
T146	130473	0	0	0
T147	943954	0	0	0
T148	431819	0	0	0
T149	3729	0	0	0
T150	222622	0	0	0
T151	385692	0	0	0
T152	186280	0	0	0
T153	315888	0	0	0
T161	0	5	0	0