Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

256273748

1

T1

553426

T2

871

T3

124593

full_word

199350023

1

T1

358832

T2

2565

T3

100247

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	455623421	1			T1	912258		T2	3436		T3	224840
auto[TlIntgErrCmd]	114	1			T129	8		T130	3		T131	3
auto[TlIntgErrData]	115	1			T129	5		T130	4		T131	5
auto[TlIntgErrBoth]	121	1			T129	7		T130	13		T131	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

240052199

1

T1

465553

T2

2605

T3

121531

auto[1]

215571572

1

T1

446705

T2

831

T3

103309

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrCmd]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	152973682	1			T1	332387		T2	541		T3	76728
auto[TlIntgErrNone]	partial	auto[1]	103299745	1			T1	221039		T2	330		T3	47865
auto[TlIntgErrNone]	full_word	auto[0]	87078354	1			T1	133166		T2	2064		T3	44803
auto[TlIntgErrNone]	full_word	auto[1]	112271640	1			T1	225666		T2	501		T3	55444
auto[TlIntgErrCmd]	partial	auto[0]	52	1			T129	2		T130	3		T164	4
auto[TlIntgErrCmd]	partial	auto[1]	56	1			T129	5		T131	2		T164	5
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T129	1		T131	1		T165	1
auto[TlIntgErrData]	partial	auto[0]	58	1			T129	3		T130	2		T131	2
auto[TlIntgErrData]	partial	auto[1]	48	1			T129	2		T130	2		T131	3
auto[TlIntgErrData]	full_word	auto[0]	5	1			T166	1		T167	2		T168	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T169	1		T170	1		T171	1
auto[TlIntgErrBoth]	partial	auto[0]	41	1			T129	2		T130	7		T131	1
auto[TlIntgErrBoth]	partial	auto[1]	66	1			T129	3		T130	5		T164	3
auto[TlIntgErrBoth]	full_word	auto[0]	7	1			T129	1		T164	1		T135	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T129	1		T130	1		T131	1