Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	96.27	93.33	100.00	92.31	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	319284	0	0
entropy_period_rd_A	2147483647	2242	0	0
intr_enable_rd_A	2147483647	3009	0	0
prefix_0_rd_A	2147483647	1856	0	0
prefix_10_rd_A	2147483647	1885	0	0
prefix_1_rd_A	2147483647	1910	0	0
prefix_2_rd_A	2147483647	1747	0	0
prefix_3_rd_A	2147483647	1856	0	0
prefix_4_rd_A	2147483647	1839	0	0
prefix_5_rd_A	2147483647	1835	0	0
prefix_6_rd_A	2147483647	1908	0	0
prefix_7_rd_A	2147483647	1928	0	0
prefix_8_rd_A	2147483647	1965	0	0
prefix_9_rd_A	2147483647	1825	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	319284	0	0
T4	1491	0	0	0
T17	609311	62987	0	0
T18	6568	0	0	0
T19	30122	0	0	0
T21	79611	0	0	0
T23	229959	0	0	0
T32	0	52664	0	0
T38	494752	0	0	0
T42	482628	0	0	0
T47	0	21315	0	0
T59	121253	0	0	0
T60	136094	0	0	0
T115	0	35379	0	0
T116	0	69980	0	0
T117	0	41985	0	0
T118	0	32383	0	0
T119	0	34	0	0
T120	0	3	0	0
T121	0	98	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2242	0	0
T88	13229	79	0	0
T93	3077	8	0	0
T120	7500	12	0	0
T131	12681	45	0	0
T136	2018	1	0	0
T137	11040	30	0	0
T138	2854	8	0	0
T139	3181	13	0	0
T140	7321	14	0	0
T141	7646	19	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3009	0	0
T88	13229	86	0	0
T120	7500	12	0	0
T131	12681	91	0	0
T136	2018	10	0	0
T137	11040	44	0	0
T138	2854	20	0	0
T139	3181	9	0	0
T140	7321	24	0	0
T142	1712	12	0	0
T143	1248	21	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1856	0	0
T88	13229	57	0	0
T93	3077	1	0	0
T120	7500	5	0	0
T131	12681	33	0	0
T136	2018	8	0	0
T137	11040	33	0	0
T138	2854	6	0	0
T139	3181	11	0	0
T140	7321	6	0	0
T142	1712	9	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1885	0	0
T88	13229	62	0	0
T120	7500	9	0	0
T131	12681	45	0	0
T136	2018	1	0	0
T137	11040	38	0	0
T138	2854	12	0	0
T139	3181	16	0	0
T140	7321	10	0	0
T141	7646	29	0	0
T144	5428	2	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1910	0	0
T88	13229	67	0	0
T93	3077	14	0	0
T120	7500	12	0	0
T131	12681	51	0	0
T136	2018	1	0	0
T137	11040	19	0	0
T138	2854	9	0	0
T139	3181	4	0	0
T140	7321	9	0	0
T142	1712	7	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1747	0	0
T88	13229	63	0	0
T93	3077	9	0	0
T120	7500	4	0	0
T131	12681	39	0	0
T136	2018	8	0	0
T137	11040	17	0	0
T138	2854	10	0	0
T140	7321	12	0	0
T141	7646	8	0	0
T145	4599	9	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1856	0	0
T88	13229	74	0	0
T93	3077	8	0	0
T120	7500	3	0	0
T131	12681	46	0	0
T137	11040	67	0	0
T138	2854	4	0	0
T139	3181	8	0	0
T140	7321	4	0	0
T141	7646	6	0	0
T142	1712	1	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1839	0	0
T88	13229	68	0	0
T93	3077	14	0	0
T120	7500	13	0	0
T131	12681	29	0	0
T136	2018	1	0	0
T137	11040	40	0	0
T138	2854	3	0	0
T139	3181	10	0	0
T140	7321	1	0	0
T142	1712	1	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1835	0	0
T88	13229	61	0	0
T93	3077	8	0	0
T120	7500	12	0	0
T131	12681	33	0	0
T136	2018	3	0	0
T137	11040	41	0	0
T138	2854	7	0	0
T139	3181	14	0	0
T140	7321	5	0	0
T142	1712	1	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1908	0	0
T88	13229	86	0	0
T93	3077	3	0	0
T120	7500	12	0	0
T131	12681	44	0	0
T136	2018	5	0	0
T137	11040	81	0	0
T138	2854	7	0	0
T139	3181	10	0	0
T140	7321	9	0	0
T142	1712	4	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1928	0	0
T88	13229	55	0	0
T93	3077	7	0	0
T120	7500	8	0	0
T131	12681	48	0	0
T136	2018	4	0	0
T137	11040	41	0	0
T138	2854	3	0	0
T139	3181	8	0	0
T140	7321	8	0	0
T142	1712	4	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1965	0	0
T88	13229	68	0	0
T120	7500	1	0	0
T131	12681	43	0	0
T136	2018	5	0	0
T137	11040	34	0	0
T138	2854	10	0	0
T139	3181	12	0	0
T140	7321	7	0	0
T141	7646	20	0	0
T142	1712	6	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1825	0	0
T88	13229	70	0	0
T93	3077	9	0	0
T131	12681	35	0	0
T136	2018	7	0	0
T137	11040	34	0	0
T138	2854	14	0	0
T139	3181	4	0	0
T140	7321	9	0	0
T141	7646	26	0	0
T142	1712	4	0	0