Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

259309133

1

T1

369894

T2

555033

T3

37

full_word

201764061

1

T1

355491

T2

359207

T3

188

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	461072874	1			T1	725385		T2	914240		T3	225
auto[TlIntgErrCmd]	106	1			T126	2		T127	7		T128	2
auto[TlIntgErrData]	107	1			T126	3		T127	2		T128	6
auto[TlIntgErrBoth]	107	1			T126	5		T127	1		T128	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

242369274

1

T1

411341

T2

466557

T3

110

auto[1]

218703920

1

T1

314044

T2

447683

T3

115

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	154409877	1			T1	227942		T2	332975		T3	14
auto[TlIntgErrNone]	partial	auto[1]	104898964	1			T1	141952		T2	222058		T3	23
auto[TlIntgErrNone]	full_word	auto[0]	87959257	1			T1	183399		T2	133582		T3	96
auto[TlIntgErrNone]	full_word	auto[1]	113804776	1			T1	172092		T2	225625		T3	92
auto[TlIntgErrCmd]	partial	auto[0]	36	1			T127	2		T128	1		T155	4
auto[TlIntgErrCmd]	partial	auto[1]	58	1			T126	2		T127	4		T128	1
auto[TlIntgErrCmd]	full_word	auto[0]	7	1			T127	1		T189	1		T190	2
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T185	2		T191	1		T192	1
auto[TlIntgErrData]	partial	auto[0]	42	1			T126	2		T127	1		T128	3
auto[TlIntgErrData]	partial	auto[1]	54	1			T126	1		T128	3		T155	7
auto[TlIntgErrData]	full_word	auto[0]	3	1			T191	1		T189	1		T193	1
auto[TlIntgErrData]	full_word	auto[1]	8	1			T127	1		T158	2		T186	1
auto[TlIntgErrBoth]	partial	auto[0]	50	1			T126	3		T155	2		T185	4
auto[TlIntgErrBoth]	partial	auto[1]	52	1			T126	2		T127	1		T128	2
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T189	1		T187	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T158	1		T187	1		T193	1