Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	253274366	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

198835999

1

T1

131210

T2

185

T3

359449

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	238442376	1			T1	148036		T2	100		T3	464943
values[0x0]	102665802	1			T1	65370		T2	48		T3	214240
values[0x1]	111002187	1			T1	70298		T2	60		T3	231841

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	197437607	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

254672758

1

T1

165055

T2

187

T3

479542

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1361411	1			T1	1078		T3	3749		T4	60
valid_sources[0x01]	1385000	1			T1	1117		T2	1		T3	3698
valid_sources[0x02]	1342435	1			T1	1138		T3	3606		T4	73
valid_sources[0x03]	4044567	1			T1	1060		T2	1		T3	3601
valid_sources[0x04]	1346775	1			T1	1065		T3	3763		T4	77
valid_sources[0x05]	1430902	1			T1	1172		T3	3632		T4	77
valid_sources[0x06]	1514314	1			T1	1109		T3	3639		T4	69
valid_sources[0x07]	1336606	1			T1	1139		T2	1		T3	3582
valid_sources[0x08]	1346510	1			T1	1107		T3	3564		T4	52
valid_sources[0x09]	3397561	1			T1	1071		T2	1		T3	3688
valid_sources[0x0a]	2247257	1			T1	1093		T3	3499		T4	61
valid_sources[0x0b]	1342304	1			T1	1141		T3	3425		T4	53
valid_sources[0x0c]	1393573	1			T1	1120		T3	3755		T4	61
valid_sources[0x0d]	1353214	1			T1	1084		T3	3373		T4	67
valid_sources[0x0e]	4718869	1			T1	1113		T2	1		T3	3569
valid_sources[0x0f]	1342462	1			T1	1100		T3	3684		T4	68
valid_sources[0x10]	1345285	1			T1	1119		T2	3		T3	3558
valid_sources[0x11]	1939293	1			T1	1169		T3	3460		T4	82
valid_sources[0x12]	3786768	1			T1	1021		T2	1		T3	3423
valid_sources[0x13]	1466385	1			T1	1097		T2	5		T3	3642
valid_sources[0x14]	1832774	1			T1	1134		T2	1		T3	3475
valid_sources[0x15]	1349682	1			T1	1082		T3	3527		T4	60
valid_sources[0x16]	1345979	1			T1	1104		T3	3746		T4	76
valid_sources[0x17]	1345337	1			T1	1092		T2	1		T3	3675
valid_sources[0x18]	5800760	1			T1	1085		T3	3280		T4	62
valid_sources[0x19]	1471600	1			T1	1128		T3	3509		T4	69
valid_sources[0x1a]	1420927	1			T1	1052		T2	1		T3	3306
valid_sources[0x1b]	1492368	1			T1	1126		T2	1		T3	3680
valid_sources[0x1c]	1391903	1			T1	1087		T3	3292		T4	59
valid_sources[0x1d]	1456743	1			T1	1125		T3	3629		T4	75
valid_sources[0x1e]	2192423	1			T1	1108		T2	2		T3	3560
valid_sources[0x1f]	2261542	1			T1	1154		T2	1		T3	3609
valid_sources[0x20]	1345598	1			T1	1074		T2	2		T3	3477
valid_sources[0x21]	2402302	1			T1	1111		T2	2		T3	3615
valid_sources[0x22]	2007664	1			T1	1104		T3	3686		T4	61
valid_sources[0x23]	1591641	1			T1	1150		T2	1		T3	3688
valid_sources[0x24]	3770796	1			T1	1125		T3	3713		T4	65
valid_sources[0x25]	1338732	1			T1	1120		T2	3		T3	3694
valid_sources[0x26]	1346519	1			T1	1117		T2	2		T3	3482
valid_sources[0x27]	1350750	1			T1	1099		T2	1		T3	3503
valid_sources[0x28]	1389974	1			T1	1078		T2	1		T3	3586
valid_sources[0x29]	1345501	1			T1	1094		T2	1		T3	3461
valid_sources[0x2a]	1353518	1			T1	1084		T3	3485		T4	69
valid_sources[0x2b]	2280481	1			T1	1076		T3	3452		T4	51
valid_sources[0x2c]	1342684	1			T1	1179		T2	1		T3	3397
valid_sources[0x2d]	1446319	1			T1	1142		T3	3529		T4	69
valid_sources[0x2e]	3789098	1			T1	1113		T3	3292		T4	69
valid_sources[0x2f]	1341148	1			T1	1104		T3	3551		T4	82
valid_sources[0x30]	1417500	1			T1	1065		T3	3290		T4	60
valid_sources[0x31]	1346091	1			T1	1103		T3	3811		T4	62
valid_sources[0x32]	1334784	1			T1	1070		T3	3597		T4	71
valid_sources[0x33]	2125851	1			T1	1099		T3	3302		T4	60
valid_sources[0x34]	1338031	1			T1	1087		T2	1		T3	3244
valid_sources[0x35]	1346950	1			T1	1123		T3	3513		T4	53
valid_sources[0x36]	1391280	1			T1	1151		T2	3		T3	3450
valid_sources[0x37]	3466954	1			T1	1087		T2	1		T3	3674
valid_sources[0x38]	1341632	1			T1	1054		T3	3966		T4	53
valid_sources[0x39]	2295352	1			T1	1134		T2	3		T3	3513
valid_sources[0x3a]	1340062	1			T1	1112		T2	1		T3	3530
valid_sources[0x3b]	2267237	1			T1	1090		T3	3650		T4	62
valid_sources[0x3c]	1344061	1			T1	1085		T2	2		T3	3665
valid_sources[0x3d]	1345351	1			T1	1134		T3	3579		T4	58
valid_sources[0x3e]	1808271	1			T1	1125		T3	3646		T4	74
valid_sources[0x3f]	1807706	1			T1	1087		T2	5		T3	3502
valid_sources[0x40]	1377380	1			T1	1129		T3	3542		T4	67
valid_sources[0x41]	1344855	1			T1	1113		T2	1		T3	3374
valid_sources[0x42]	1350732	1			T1	1132		T2	2		T3	3625
valid_sources[0x43]	3775490	1			T1	1094		T3	3367		T4	74
valid_sources[0x44]	1497376	1			T1	1172		T3	3525		T4	45
valid_sources[0x45]	1353923	1			T1	1134		T2	2		T3	3559
valid_sources[0x46]	1514191	1			T1	1044		T2	1		T3	3726
valid_sources[0x47]	1336084	1			T1	1004		T3	3434		T4	56
valid_sources[0x48]	1341243	1			T1	1075		T2	1		T3	3533
valid_sources[0x49]	1371981	1			T1	1112		T3	3481		T4	61
valid_sources[0x4a]	1382372	1			T1	1104		T2	3		T3	3382
valid_sources[0x4b]	1336710	1			T1	1143		T2	1		T3	3637
valid_sources[0x4c]	1340745	1			T1	1086		T3	3573		T4	47
valid_sources[0x4d]	1372376	1			T1	1077		T2	1		T3	3436
valid_sources[0x4e]	1339735	1			T1	1113		T2	3		T3	3540
valid_sources[0x4f]	1532768	1			T1	1113		T2	4		T3	3652
valid_sources[0x50]	1915465	1			T1	1083		T2	1		T3	3606
valid_sources[0x51]	1340768	1			T1	1084		T3	3702		T4	61
valid_sources[0x52]	3326009	1			T1	1135		T2	1		T3	3446
valid_sources[0x53]	1449574	1			T1	1062		T2	2		T3	3638
valid_sources[0x54]	3746270	1			T1	1100		T3	3734		T4	73
valid_sources[0x55]	1343160	1			T1	1094		T2	1		T3	3675
valid_sources[0x56]	2010734	1			T1	1157		T2	1		T3	3512
valid_sources[0x57]	1346512	1			T1	1123		T3	3711		T4	72
valid_sources[0x58]	2336622	1			T1	1084		T2	2		T3	3730
valid_sources[0x59]	1339932	1			T1	1096		T3	3504		T4	64
valid_sources[0x5a]	1346274	1			T1	1070		T2	2		T3	3419
valid_sources[0x5b]	1401582	1			T1	1094		T3	3498		T4	70
valid_sources[0x5c]	1384028	1			T1	1132		T2	2		T3	3317
valid_sources[0x5d]	1340395	1			T1	1090		T3	3596		T4	64
valid_sources[0x5e]	1341707	1			T1	1127		T2	1		T3	3524
valid_sources[0x5f]	1357138	1			T1	1080		T3	3693		T4	71
valid_sources[0x60]	1346804	1			T1	1103		T3	3708		T4	61
valid_sources[0x61]	1339975	1			T1	1097		T2	1		T3	3677
valid_sources[0x62]	4637044	1			T1	1132		T2	1		T3	3559
valid_sources[0x63]	1342236	1			T1	1105		T2	2		T3	3462
valid_sources[0x64]	3381479	1			T1	1107		T3	3661		T4	87
valid_sources[0x65]	1342057	1			T1	1094		T3	3858		T4	83
valid_sources[0x66]	1355202	1			T1	1111		T3	3337		T4	53
valid_sources[0x67]	3785084	1			T1	1186		T3	3682		T4	74
valid_sources[0x68]	1431251	1			T1	1165		T2	1		T3	3487
valid_sources[0x69]	1411259	1			T1	1129		T3	3432		T4	62
valid_sources[0x6a]	1345120	1			T1	1084		T3	3697		T4	58
valid_sources[0x6b]	1340242	1			T1	1113		T3	3499		T4	46
valid_sources[0x6c]	1347518	1			T1	1072		T2	2		T3	3411
valid_sources[0x6d]	1331066	1			T1	1117		T3	3417		T4	56
valid_sources[0x6e]	3745672	1			T1	1132		T3	3408		T4	80
valid_sources[0x6f]	1372649	1			T1	1134		T3	3424		T4	85
valid_sources[0x70]	1358923	1			T1	1101		T2	1		T3	3450
valid_sources[0x71]	1346485	1			T1	1100		T3	3801		T4	79
valid_sources[0x72]	1445188	1			T1	1091		T3	3566		T4	56
valid_sources[0x73]	1341598	1			T1	1066		T2	3		T3	3428
valid_sources[0x74]	2100236	1			T1	1078		T3	3461		T4	80
valid_sources[0x75]	1341074	1			T1	1140		T3	3730		T20	2
valid_sources[0x76]	1998335	1			T1	1116		T3	3615		T4	55
valid_sources[0x77]	3739672	1			T1	1109		T3	3389		T4	67
valid_sources[0x78]	1364683	1			T1	1112		T3	3374		T4	71
valid_sources[0x79]	1338746	1			T1	1135		T3	3402		T4	59
valid_sources[0x7a]	3804928	1			T1	1128		T2	5		T3	3491
valid_sources[0x7b]	1375641	1			T1	1151		T3	3507		T4	56
valid_sources[0x7c]	1360512	1			T1	1147		T3	3741		T4	43
valid_sources[0x7d]	1345704	1			T1	1086		T2	1		T3	3627
valid_sources[0x7e]	1339868	1			T1	1093		T3	3553		T4	70
valid_sources[0x7f]	1345252	1			T1	1126		T3	3523		T4	56
valid_sources[0x80]	1342898	1			T1	1100		T2	3		T3	3427

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

86508251

1

T1

57590

T2

90

T3

133310

values[0x0]

all_enables

biggest_size

60426595

1

T1

39463

T2

42

T3

122387

values[0x1]

all_enables

biggest_size

51901153

1

T1

34157

T2

53

T3

103752