Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

254385350

1

T1

152494

T2

23

T3

551575

full_word

198906342

1

T1

131210

T2

185

T3

359449

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	453291422	1			T1	283704		T2	208		T3	911024
auto[TlIntgErrCmd]	89	1			T122	6		T123	7		T124	1
auto[TlIntgErrData]	84	1			T122	1		T123	5		T124	6
auto[TlIntgErrBoth]	97	1			T122	3		T123	8		T124	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

238661281

1

T1

148036

T2

100

T3

464943

auto[1]

214630411

1

T1

135668

T2

108

T3

446081

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	152134943	1			T1	90446		T2	10		T3	331633
auto[TlIntgErrNone]	partial	auto[1]	102250177	1			T1	62048		T2	13		T3	219942
auto[TlIntgErrNone]	full_word	auto[0]	86526209	1			T1	57590		T2	90		T3	133310
auto[TlIntgErrNone]	full_word	auto[1]	112380093	1			T1	73620		T2	95		T3	226139
auto[TlIntgErrCmd]	partial	auto[0]	34	1			T122	1		T123	3		T180	1
auto[TlIntgErrCmd]	partial	auto[1]	38	1			T122	4		T123	3		T124	1
auto[TlIntgErrCmd]	full_word	auto[0]	9	1			T180	1		T188	1		T189	1
auto[TlIntgErrCmd]	full_word	auto[1]	8	1			T122	1		T123	1		T167	1
auto[TlIntgErrData]	partial	auto[0]	38	1			T122	1		T123	2		T124	1
auto[TlIntgErrData]	partial	auto[1]	36	1			T123	3		T124	5		T167	1
auto[TlIntgErrData]	full_word	auto[0]	3	1			T167	1		T190	1		T191	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T167	1		T180	1		T181	1
auto[TlIntgErrBoth]	partial	auto[0]	39	1			T122	2		T123	5		T124	1
auto[TlIntgErrBoth]	partial	auto[1]	45	1			T122	1		T123	1		T124	2
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T123	2		T167	1		T192	3
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T181	2		T189	1		T185	1