Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	258831	0	0
entropy_period_rd_A	2147483647	1636	0	0
intr_enable_rd_A	2147483647	2289	0	0
prefix_0_rd_A	2147483647	1720	0	0
prefix_10_rd_A	2147483647	1690	0	0
prefix_1_rd_A	2147483647	1689	0	0
prefix_2_rd_A	2147483647	1691	0	0
prefix_3_rd_A	2147483647	1645	0	0
prefix_4_rd_A	2147483647	1701	0	0
prefix_5_rd_A	2147483647	1565	0	0
prefix_6_rd_A	2147483647	1594	0	0
prefix_7_rd_A	2147483647	1676	0	0
prefix_8_rd_A	2147483647	1614	0	0
prefix_9_rd_A	2147483647	1789	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	258831	0	0
T33	0	17007	0	0
T43	204180	26621	0	0
T52	0	58347	0	0
T88	411348	0	0	0
T122	0	2	0	0
T128	0	23683	0	0
T129	0	114287	0	0
T130	0	16103	0	0
T131	0	142	0	0
T133	0	53	0	0
T134	0	8	0	0
T135	1385	0	0	0
T136	1106	0	0	0
T137	153504	0	0	0
T138	174357	0	0	0
T139	38559	0	0	0
T140	128533	0	0	0
T141	1563	0	0	0
T142	672363	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1636	0	0
T134	8167	6	0	0
T153	2404	9	0	0
T154	2168	3	0	0
T155	2664	6	0	0
T156	26153	245	0	0
T157	143460	231	0	0
T158	6127	12	0	0
T159	10187	9	0	0
T160	25116	245	0	0
T161	10192	36	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2289	0	0
T127	1076	11	0	0
T134	8167	22	0	0
T153	2404	12	0	0
T154	2168	6	0	0
T155	2664	23	0	0
T156	26153	205	0	0
T157	143460	471	0	0
T162	867	15	0	0
T163	1179	17	0	0
T164	1819	18	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1720	0	0
T134	8167	23	0	0
T153	2404	7	0	0
T154	2168	1	0	0
T155	2664	12	0	0
T156	26153	237	0	0
T157	143460	459	0	0
T158	6127	5	0	0
T159	10187	56	0	0
T160	25116	199	0	0
T165	2365	4	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1690	0	0
T134	8167	24	0	0
T153	2404	2	0	0
T155	2664	4	0	0
T156	26153	210	0	0
T157	143460	439	0	0
T158	6127	1	0	0
T159	10187	13	0	0
T160	25116	253	0	0
T161	10192	29	0	0
T165	2365	7	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1689	0	0
T134	8167	3	0	0
T153	2404	9	0	0
T155	2664	6	0	0
T156	26153	198	0	0
T157	143460	431	0	0
T158	6127	15	0	0
T159	10187	35	0	0
T160	25116	238	0	0
T161	10192	29	0	0
T165	2365	14	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1691	0	0
T134	8167	16	0	0
T153	2404	8	0	0
T154	2168	4	0	0
T155	2664	9	0	0
T156	26153	247	0	0
T157	143460	397	0	0
T158	6127	7	0	0
T159	10187	35	0	0
T160	25116	171	0	0
T165	2365	2	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1645	0	0
T134	8167	20	0	0
T153	2404	9	0	0
T154	2168	4	0	0
T155	2664	7	0	0
T156	26153	237	0	0
T157	143460	457	0	0
T158	6127	6	0	0
T159	10187	6	0	0
T160	25116	205	0	0
T165	2365	8	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1701	0	0
T134	8167	4	0	0
T153	2404	5	0	0
T155	2664	7	0	0
T156	26153	219	0	0
T157	143460	529	0	0
T158	6127	9	0	0
T159	10187	24	0	0
T160	25116	204	0	0
T161	10192	18	0	0
T166	1935	7	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1565	0	0
T134	8167	8	0	0
T153	2404	4	0	0
T155	2664	6	0	0
T156	26153	230	0	0
T157	143460	452	0	0
T158	6127	10	0	0
T159	10187	19	0	0
T160	25116	207	0	0
T161	10192	30	0	0
T165	2365	2	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1594	0	0
T134	8167	16	0	0
T153	2404	3	0	0
T155	2664	7	0	0
T156	26153	193	0	0
T157	143460	421	0	0
T158	6127	20	0	0
T159	10187	13	0	0
T160	25116	214	0	0
T161	10192	38	0	0
T165	2365	6	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1676	0	0
T134	8167	17	0	0
T153	2404	11	0	0
T154	2168	6	0	0
T155	2664	9	0	0
T156	26153	224	0	0
T157	143460	472	0	0
T158	6127	15	0	0
T159	10187	15	0	0
T160	25116	200	0	0
T161	10192	31	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1614	0	0
T134	8167	16	0	0
T153	2404	2	0	0
T154	2168	5	0	0
T155	2664	1	0	0
T156	26153	197	0	0
T157	143460	435	0	0
T158	6127	12	0	0
T159	10187	30	0	0
T160	25116	239	0	0
T165	2365	11	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1789	0	0
T134	8167	20	0	0
T153	2404	4	0	0
T155	2664	12	0	0
T156	26153	238	0	0
T157	143460	443	0	0
T159	10187	20	0	0
T160	25116	278	0	0
T161	10192	24	0	0
T165	2365	5	0	0
T167	13216	53	0	0