Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	254434928	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

198964592

1

T1

23363

T2

100127

T3

184126

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	239280160	1			T1	18204		T2	128983		T3	234593
values[0x0]	102828004	1			T1	4486		T2	557503		T3	105846
values[0x1]	111291356	1			T1	4589		T2	608419		T3	114644

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	198283732	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

255115788

1

T1

24361

T2

132338

T3

242751

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1391987	1			T1	65		T2	10105		T3	1738
valid_sources[0x01]	2319623	1			T1	87		T2	10292		T3	1748
valid_sources[0x02]	1392754	1			T1	121		T2	7793		T3	1809
valid_sources[0x03]	2057477	1			T1	176		T2	9874		T3	1685
valid_sources[0x04]	1390578	1			T1	70		T2	9870		T3	1723
valid_sources[0x05]	1396752	1			T1	82		T2	9690		T3	1746
valid_sources[0x06]	1469816	1			T1	167		T2	9035		T3	1890
valid_sources[0x07]	1505648	1			T1	202		T2	9916		T3	1716
valid_sources[0x08]	2022629	1			T1	171		T2	9799		T3	1769
valid_sources[0x09]	2277448	1			T1	107		T2	9031		T3	1812
valid_sources[0x0a]	1392322	1			T1	51		T2	10332		T3	1829
valid_sources[0x0b]	1420305	1			T1	82		T2	9993		T3	1745
valid_sources[0x0c]	1428780	1			T1	99		T2	9356		T3	1732
valid_sources[0x0d]	1408080	1			T1	168		T2	9268		T3	1813
valid_sources[0x0e]	2076583	1			T1	13		T2	10943		T3	1725
valid_sources[0x0f]	1381505	1			T1	27		T2	9184		T3	1902
valid_sources[0x10]	1390620	1			T1	84		T2	8556		T3	1781
valid_sources[0x11]	1849816	1			T1	35		T2	9387		T3	1863
valid_sources[0x12]	1616263	1			T1	107		T2	9719		T3	1788
valid_sources[0x13]	1853487	1			T1	150		T2	10135		T3	1771
valid_sources[0x14]	1391147	1			T1	33		T2	11028		T3	1713
valid_sources[0x15]	2237387	1			T1	119		T2	9185		T3	1863
valid_sources[0x16]	2148663	1			T1	25		T2	9935		T3	1705
valid_sources[0x17]	1389042	1			T1	68		T2	10422		T3	1751
valid_sources[0x18]	1392552	1			T1	17		T2	10038		T3	1833
valid_sources[0x19]	1389121	1			T1	49		T2	8706		T3	1751
valid_sources[0x1a]	1390633	1			T1	147		T2	8874		T3	1769
valid_sources[0x1b]	3789192	1			T1	70		T2	9765		T3	1757
valid_sources[0x1c]	1386777	1			T1	210		T2	10030		T3	1757
valid_sources[0x1d]	1392018	1			T1	27		T2	10398		T3	1745
valid_sources[0x1e]	1386061	1			T1	83		T2	9181		T3	1865
valid_sources[0x1f]	1695069	1			T1	69		T2	8327		T3	1833
valid_sources[0x20]	1388852	1			T1	113		T2	8843		T3	1844
valid_sources[0x21]	1397060	1			T1	162		T2	9913		T3	1758
valid_sources[0x22]	2309361	1			T1	37		T2	10023		T3	1722
valid_sources[0x23]	1468344	1			T1	78		T2	10137		T3	1779
valid_sources[0x24]	1384537	1			T1	50		T2	9010		T3	1851
valid_sources[0x25]	1390529	1			T1	187		T2	8993		T3	1718
valid_sources[0x26]	1382333	1			T1	110		T2	9384		T3	1775
valid_sources[0x27]	1385557	1			T1	114		T2	10133		T3	1844
valid_sources[0x28]	1393447	1			T1	127		T2	10714		T3	1691
valid_sources[0x29]	1418683	1			T1	60		T2	8956		T3	1795
valid_sources[0x2a]	2720494	1			T1	148		T2	9577		T3	1799
valid_sources[0x2b]	1390315	1			T1	141		T2	9532		T3	1715
valid_sources[0x2c]	1394555	1			T1	98		T2	10430		T3	1744
valid_sources[0x2d]	1688999	1			T1	119		T2	10060		T3	1846
valid_sources[0x2e]	1392834	1			T1	214		T2	8460		T3	1719
valid_sources[0x2f]	1393444	1			T1	140		T2	9730		T3	1792
valid_sources[0x30]	1434407	1			T1	85		T2	10076		T3	1835
valid_sources[0x31]	1395012	1			T1	124		T2	9978		T3	1722
valid_sources[0x32]	1392936	1			T1	37		T2	9936		T3	1856
valid_sources[0x33]	3429506	1			T1	109		T2	9827		T3	1771
valid_sources[0x34]	1887413	1			T1	51		T2	9254		T3	1794
valid_sources[0x35]	1475293	1			T1	140		T2	8958		T3	1825
valid_sources[0x36]	1429270	1			T1	82		T2	9169		T3	1761
valid_sources[0x37]	1393201	1			T1	123		T2	8894		T3	1779
valid_sources[0x38]	1388568	1			T1	46		T2	9518		T3	1803
valid_sources[0x39]	1521537	1			T1	159		T2	9837		T3	1869
valid_sources[0x3a]	1393006	1			T1	68		T2	9722		T3	1821
valid_sources[0x3b]	1555110	1			T1	129		T2	10034		T3	1750
valid_sources[0x3c]	1389142	1			T1	82		T2	9912		T3	1773
valid_sources[0x3d]	2276275	1			T1	87		T2	9821		T3	1712
valid_sources[0x3e]	1401798	1			T1	59		T2	9870		T3	1625
valid_sources[0x3f]	1383952	1			T1	50		T2	8994		T3	1776
valid_sources[0x40]	1396435	1			T1	100		T2	10045		T3	1811
valid_sources[0x41]	1386514	1			T1	89		T2	9806		T3	1773
valid_sources[0x42]	3865273	1			T1	114		T2	10101		T3	1743
valid_sources[0x43]	1390178	1			T1	250		T2	8658		T3	1811
valid_sources[0x44]	1566642	1			T1	140		T2	9943		T3	1840
valid_sources[0x45]	1389185	1			T1	52		T2	9352		T3	1795
valid_sources[0x46]	1464734	1			T1	129		T2	10432		T3	1820
valid_sources[0x47]	1387663	1			T1	89		T2	9598		T3	1796
valid_sources[0x48]	1393891	1			T1	37		T2	10653		T3	1692
valid_sources[0x49]	3818675	1			T1	144		T2	10865		T3	1792
valid_sources[0x4a]	1404340	1			T1	99		T2	10204		T3	1734
valid_sources[0x4b]	2250852	1			T1	43		T2	8606		T3	1836
valid_sources[0x4c]	1404060	1			T1	193		T2	10091		T3	1704
valid_sources[0x4d]	2055911	1			T1	116		T2	8582		T3	1730
valid_sources[0x4e]	1392781	1			T1	138		T2	9474		T3	1867
valid_sources[0x4f]	1485906	1			T1	55		T2	9268		T3	1763
valid_sources[0x50]	1389269	1			T1	90		T2	9632		T3	1763
valid_sources[0x51]	1392959	1			T1	146		T2	9777		T3	1771
valid_sources[0x52]	1395046	1			T1	163		T2	9575		T3	1819
valid_sources[0x53]	1397025	1			T1	104		T2	9577		T3	1807
valid_sources[0x54]	1389202	1			T1	41		T2	9925		T3	1860
valid_sources[0x55]	1530879	1			T1	13		T2	9879		T3	1752
valid_sources[0x56]	2333288	1			T1	75		T2	9618		T3	1777
valid_sources[0x57]	1390823	1			T1	76		T2	9140		T3	1786
valid_sources[0x58]	1385255	1			T1	59		T2	8715		T3	1746
valid_sources[0x59]	1389464	1			T1	70		T2	9274		T3	1688
valid_sources[0x5a]	1396561	1			T1	249		T2	9639		T3	1785
valid_sources[0x5b]	2268295	1			T1	77		T2	8228		T3	1762
valid_sources[0x5c]	2731389	1			T1	31		T2	9533		T3	1754
valid_sources[0x5d]	3430636	1			T1	64		T2	8727		T3	1763
valid_sources[0x5e]	1394892	1			T1	62		T2	10053		T3	1797
valid_sources[0x5f]	1392293	1			T1	79		T2	9660		T3	1773
valid_sources[0x60]	3798034	1			T1	69		T2	10656		T3	1886
valid_sources[0x61]	2254286	1			T1	146		T2	9412		T3	1823
valid_sources[0x62]	3698595	1			T1	123		T2	9280		T3	1755
valid_sources[0x63]	3466157	1			T1	50		T2	10296		T3	1816
valid_sources[0x64]	1393420	1			T1	139		T2	9982		T3	1760
valid_sources[0x65]	1386135	1			T1	90		T2	9927		T3	1844
valid_sources[0x66]	1402030	1			T1	111		T2	9320		T3	1722
valid_sources[0x67]	1862441	1			T1	145		T2	9825		T3	1800
valid_sources[0x68]	1382306	1			T1	97		T2	9319		T3	1756
valid_sources[0x69]	1384682	1			T1	159		T2	9334		T3	1763
valid_sources[0x6a]	2269646	1			T1	141		T2	9580		T3	1787
valid_sources[0x6b]	1496271	1			T1	138		T2	10219		T3	1760
valid_sources[0x6c]	1755192	1			T1	107		T2	9655		T3	1749
valid_sources[0x6d]	1424125	1			T1	182		T2	9927		T3	1818
valid_sources[0x6e]	1853619	1			T1	66		T2	9421		T3	1841
valid_sources[0x6f]	1941689	1			T1	32		T2	9862		T3	1714
valid_sources[0x70]	1968537	1			T1	123		T2	9989		T3	1671
valid_sources[0x71]	1377332	1			T1	79		T2	8624		T3	1743
valid_sources[0x72]	1564793	1			T1	135		T2	9408		T3	1756
valid_sources[0x73]	1388567	1			T1	80		T2	8772		T3	1783
valid_sources[0x74]	1432824	1			T1	170		T2	8435		T3	1812
valid_sources[0x75]	2328041	1			T1	155		T2	9472		T3	1769
valid_sources[0x76]	1388831	1			T1	157		T2	10113		T3	1783
valid_sources[0x77]	2295171	1			T1	149		T2	9836		T3	1946
valid_sources[0x78]	1384559	1			T1	114		T2	10576		T3	1730
valid_sources[0x79]	3788497	1			T1	61		T2	9826		T3	1697
valid_sources[0x7a]	1414117	1			T1	90		T2	8852		T3	1739
valid_sources[0x7b]	1392969	1			T1	123		T2	10711		T3	1732
valid_sources[0x7c]	1382958	1			T1	222		T2	9254		T3	1744
valid_sources[0x7d]	4458783	1			T1	83		T2	10433		T3	1753
valid_sources[0x7e]	1381531	1			T1	190		T2	9962		T3	1824
valid_sources[0x7f]	1389052	1			T1	192		T2	8699		T3	1764
valid_sources[0x80]	1387900	1			T1	271		T2	8761		T3	1760

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

86712793

1

T1

16016

T2

431568

T3

70828

values[0x0]

all_enables

biggest_size

60401061

1

T1

3724

T2

309538

T3

61018

values[0x1]

all_enables

biggest_size

51850738

1

T1

3623

T2

260164

T3

52280