Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

256609788

1

T1

3916

T2

145448

T3

270957

full_word

199101171

1

T1

23363

T2

100127

T3

184126

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	455710679	1			T1	27279		T2	245575		T3	455083
auto[TlIntgErrCmd]	106	1			T106	7		T107	3		T108	2
auto[TlIntgErrData]	94	1			T106	7		T107	2		T108	4
auto[TlIntgErrBoth]	80	1			T106	6		T107	5		T108	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

239707157

1

T1

18204

T2

128983

T3

234593

auto[1]

216003802

1

T1

9075

T2

116592

T3

220490

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	152959860	1			T1	2188		T2	858264		T3	163765
auto[TlIntgErrNone]	partial	auto[1]	103649675	1			T1	1728		T2	596220		T3	107192
auto[TlIntgErrNone]	full_word	auto[0]	86747170	1			T1	16016		T2	431568		T3	70828
auto[TlIntgErrNone]	full_word	auto[1]	112353974	1			T1	7347		T2	569702		T3	113298
auto[TlIntgErrCmd]	partial	auto[0]	42	1			T106	4		T107	3		T131	1
auto[TlIntgErrCmd]	partial	auto[1]	52	1			T106	2		T108	2		T131	2
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T158	1		T163	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	10	1			T106	1		T141	1		T164	1
auto[TlIntgErrData]	partial	auto[0]	40	1			T106	4		T108	2		T158	5
auto[TlIntgErrData]	partial	auto[1]	45	1			T106	3		T107	1		T108	1
auto[TlIntgErrData]	full_word	auto[0]	5	1			T107	1		T108	1		T141	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T131	1		T158	1		T165	1
auto[TlIntgErrBoth]	partial	auto[0]	36	1			T106	3		T107	2		T108	3
auto[TlIntgErrBoth]	partial	auto[1]	38	1			T106	2		T107	3		T108	1
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T166	1		T162	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T106	1		T164	1		T160	1