Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	506769	0	0
entropy_period_rd_A	2147483647	1525	0	0
intr_enable_rd_A	2147483647	2336	0	0
prefix_0_rd_A	2147483647	1784	0	0
prefix_10_rd_A	2147483647	1863	0	0
prefix_1_rd_A	2147483647	1689	0	0
prefix_2_rd_A	2147483647	1817	0	0
prefix_3_rd_A	2147483647	1724	0	0
prefix_4_rd_A	2147483647	1782	0	0
prefix_5_rd_A	2147483647	1720	0	0
prefix_6_rd_A	2147483647	2118	0	0
prefix_7_rd_A	2147483647	1711	0	0
prefix_8_rd_A	2147483647	1627	0	0
prefix_9_rd_A	2147483647	1855	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	506769	0	0
T5	2578	0	0	0
T20	45308	0	0	0
T24	152525	15741	0	0
T28	385474	0	0	0
T33	0	39970	0	0
T42	656614	0	0	0
T43	486217	0	0	0
T56	0	26490	0	0
T68	16837	0	0	0
T69	29215	0	0	0
T70	20591	0	0	0
T71	460145	0	0	0
T113	0	40992	0	0
T114	0	76161	0	0
T115	0	93170	0	0
T116	0	82852	0	0
T117	0	68345	0	0
T118	0	59785	0	0
T119	0	151	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1525	0	0
T92	13213	84	0	0
T95	3478	9	0	0
T107	11556	48	0	0
T131	10392	29	0	0
T132	6715	8	0	0
T133	4422	8	0	0
T134	2745	15	0	0
T135	8042	24	0	0
T136	2565	5	0	0
T137	73579	133	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2336	0	0
T92	13213	78	0	0
T95	3478	14	0	0
T107	11556	30	0	0
T131	10392	38	0	0
T132	6715	6	0	0
T133	4422	10	0	0
T134	2745	24	0	0
T138	1313	10	0	0
T139	877	10	0	0
T140	1054	17	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1784	0	0
T92	13213	68	0	0
T95	3478	6	0	0
T107	11556	38	0	0
T131	10392	13	0	0
T132	6715	17	0	0
T133	4422	5	0	0
T134	2745	1	0	0
T135	8042	12	0	0
T137	73579	220	0	0
T141	24717	92	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1863	0	0
T92	13213	67	0	0
T95	3478	10	0	0
T107	11556	40	0	0
T131	10392	17	0	0
T132	6715	41	0	0
T133	4422	3	0	0
T134	2745	13	0	0
T135	8042	15	0	0
T136	2565	9	0	0
T137	73579	246	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1689	0	0
T92	13213	45	0	0
T95	3478	7	0	0
T107	11556	39	0	0
T131	10392	19	0	0
T132	6715	6	0	0
T133	4422	8	0	0
T134	2745	5	0	0
T135	8042	10	0	0
T136	2565	4	0	0
T137	73579	236	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1817	0	0
T92	13213	50	0	0
T95	3478	14	0	0
T107	11556	43	0	0
T131	10392	24	0	0
T132	6715	8	0	0
T133	4422	6	0	0
T134	2745	7	0	0
T135	8042	19	0	0
T136	2565	5	0	0
T137	73579	222	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1724	0	0
T92	13213	60	0	0
T95	3478	8	0	0
T107	11556	31	0	0
T131	10392	17	0	0
T132	6715	10	0	0
T133	4422	11	0	0
T134	2745	11	0	0
T135	8042	15	0	0
T136	2565	8	0	0
T137	73579	240	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1782	0	0
T92	13213	50	0	0
T95	3478	17	0	0
T107	11556	33	0	0
T131	10392	5	0	0
T132	6715	8	0	0
T133	4422	6	0	0
T134	2745	14	0	0
T135	8042	18	0	0
T136	2565	10	0	0
T137	73579	214	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1720	0	0
T92	13213	60	0	0
T95	3478	16	0	0
T107	11556	44	0	0
T131	10392	18	0	0
T132	6715	20	0	0
T133	4422	2	0	0
T134	2745	15	0	0
T135	8042	11	0	0
T136	2565	11	0	0
T137	73579	224	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2118	0	0
T92	13213	37	0	0
T95	3478	11	0	0
T107	11556	47	0	0
T131	10392	35	0	0
T132	6715	19	0	0
T133	4422	8	0	0
T134	2745	16	0	0
T135	8042	21	0	0
T136	2565	2	0	0
T137	73579	225	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1711	0	0
T92	13213	63	0	0
T95	3478	18	0	0
T107	11556	56	0	0
T131	10392	21	0	0
T132	6715	4	0	0
T133	4422	5	0	0
T134	2745	11	0	0
T135	8042	11	0	0
T136	2565	3	0	0
T137	73579	223	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1627	0	0
T92	13213	65	0	0
T95	3478	20	0	0
T107	11556	42	0	0
T131	10392	7	0	0
T132	6715	4	0	0
T133	4422	12	0	0
T134	2745	8	0	0
T135	8042	24	0	0
T136	2565	2	0	0
T137	73579	194	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1855	0	0
T92	13213	44	0	0
T95	3478	12	0	0
T107	11556	37	0	0
T131	10392	18	0	0
T132	6715	26	0	0
T133	4422	5	0	0
T134	2745	4	0	0
T135	8042	18	0	0
T136	2565	6	0	0
T142	3752	8	0	0