Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

257788656

1

T1

281220

T2

553964

T3

280436

full_word

200761208

1

T1

184317

T2

358984

T3

184027

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	458549534	1			T1	465537		T2	912948		T3	464463
auto[TlIntgErrCmd]	111	1			T111	5		T112	6		T113	7
auto[TlIntgErrData]	117	1			T111	4		T112	7		T113	3
auto[TlIntgErrBoth]	102	1			T111	1		T112	7		T113	10

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

241690581

1

T1

239821

T2

465893

T3

239277

auto[1]

216859283

1

T1

225716

T2

447055

T3

225186

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	153996544	1			T1	167489		T2	332650		T3	167034
auto[TlIntgErrNone]	partial	auto[1]	103791804	1			T1	113731		T2	221314		T3	113402
auto[TlIntgErrNone]	full_word	auto[0]	87693868	1			T1	72332		T2	133243		T3	72243
auto[TlIntgErrNone]	full_word	auto[1]	113067318	1			T1	111985		T2	225741		T3	111784
auto[TlIntgErrCmd]	partial	auto[0]	57	1			T111	4		T112	4		T113	2
auto[TlIntgErrCmd]	partial	auto[1]	46	1			T111	1		T112	2		T113	4
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T161	1		T162	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T113	1		T163	2		T164	1
auto[TlIntgErrData]	partial	auto[0]	55	1			T111	1		T112	3		T113	1
auto[TlIntgErrData]	partial	auto[1]	55	1			T111	3		T112	4		T113	2
auto[TlIntgErrData]	full_word	auto[0]	4	1			T165	1		T164	1		T166	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T161	1		T167	1		T162	1
auto[TlIntgErrBoth]	partial	auto[0]	47	1			T112	4		T113	5		T133	8
auto[TlIntgErrBoth]	partial	auto[1]	48	1			T111	1		T112	2		T113	5
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T112	1		T168	2		T169	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T170	1		T171	1		T168	1