Module Definition
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Module Instance : tb.dut.u_tlul_adapter_msgfifo.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
71.04 90.91 66.67 55.56


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
71.04 90.91 66.67 55.56


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
62.12 78.57 38.46 71.43 60.00 u_sramreqfifo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_tlul_adapter_msgfifo.u_rspfifo.gen_normal_fifo.u_fifo_cnt

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
71.04 90.91 66.67 55.56


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
71.04 90.91 66.67 55.56


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
71.27 92.31 47.06 85.71 60.00 u_rspfifo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_tlul_adapter_msgfifo.u_reqfifo.gen_normal_fifo.u_fifo_cnt

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
81.58 92.00 80.00 72.73


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
81.58 92.00 80.00 72.73


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.19 100.00 68.75 100.00 100.00 u_reqfifo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_staterd.u_tlul_adapter.u_reqfifo.gen_normal_fifo.u_fifo_cnt

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
81.58 92.00 80.00 72.73


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
81.58 92.00 80.00 72.73


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.19 100.00 68.75 100.00 100.00 u_reqfifo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_staterd.u_tlul_adapter.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
81.58 92.00 80.00 72.73


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
81.58 92.00 80.00 72.73


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
90.62 100.00 62.50 100.00 100.00 u_sramreqfifo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_staterd.u_tlul_adapter.u_rspfifo.gen_normal_fifo.u_fifo_cnt

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
81.58 92.00 80.00 72.73


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
81.58 92.00 80.00 72.73


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.75 100.00 75.00 100.00 100.00 u_rspfifo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_msgfifo.u_msgfifo.gen_normal_fifo.u_fifo_cnt

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.88 100.00 87.50 100.00 100.00 u_msgfifo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_fifo_sync_cnt ( parameter Depth=1,Secure=0,PtrW=1,DepthW=1,WrapPtrW=2 )
Line Coverage for Module self-instances :
SCORELINE
81.58 92.00
tb.dut.u_tlul_adapter_msgfifo.u_reqfifo.gen_normal_fifo.u_fifo_cnt

SCORELINE
71.04 90.91
tb.dut.u_tlul_adapter_msgfifo.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt

SCORELINE
71.04 90.91
tb.dut.u_tlul_adapter_msgfifo.u_rspfifo.gen_normal_fifo.u_fifo_cnt

SCORELINE
81.58 92.00
tb.dut.u_staterd.u_tlul_adapter.u_reqfifo.gen_normal_fifo.u_fifo_cnt

SCORELINE
81.58 92.00
tb.dut.u_staterd.u_tlul_adapter.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt

SCORELINE
81.58 92.00
tb.dut.u_staterd.u_tlul_adapter.u_rspfifo.gen_normal_fifo.u_fifo_cnt

Line No.TotalCoveredPercent
TOTAL252392.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6811100.00
ALWAYS1137685.71
ALWAYS1257685.71
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
41 1 1
42 1 1
46 1 1
47 1 1
51 1 1
52 1 1
55 1 1
56 1 1
59 1 1
61 1 1
68 1 1
113 1 1
114 1 1
115 1 1
116 unreachable
117 1 1
118 1 1
119 1 1
120 0 1
MISSING_ELSE
125 1 1
126 1 1
127 1 1
128 unreachable
129 1 1
130 1 1
131 1 1
132 0 1
MISSING_ELSE


Line Coverage for Module : prim_fifo_sync_cnt ( parameter Depth=10,Secure=0,PtrW=4,DepthW=4,WrapPtrW=5 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_msgfifo.u_msgfifo.gen_normal_fifo.u_fifo_cnt

Line No.TotalCoveredPercent
TOTAL2727100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6811100.00
ALWAYS11388100.00
ALWAYS12588100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
41 1 1
42 1 1
46 1 1
47 1 1
51 1 1
52 1 1
55 1 1
56 1 1
59 1 1
61 1 1
68 1 1
113 1 1
114 1 1
115 1 1
116 1 1
117 1 1
118 1 1
119 1 1
120 1 1
MISSING_ELSE
125 1 1
126 1 1
127 1 1
128 1 1
129 1 1
130 1 1
131 1 1
132 1 1
MISSING_ELSE


Cond Coverage for Module : prim_fifo_sync_cnt ( parameter Depth=1,Secure=0,PtrW=1,DepthW=1,WrapPtrW=2 )
Cond Coverage for Module self-instances :
SCORECOND
81.58 80.00
tb.dut.u_tlul_adapter_msgfifo.u_reqfifo.gen_normal_fifo.u_fifo_cnt

SCORECOND
71.04 66.67
tb.dut.u_tlul_adapter_msgfifo.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt

SCORECOND
71.04 66.67
tb.dut.u_tlul_adapter_msgfifo.u_rspfifo.gen_normal_fifo.u_fifo_cnt

SCORECOND
81.58 80.00
tb.dut.u_staterd.u_tlul_adapter.u_reqfifo.gen_normal_fifo.u_fifo_cnt

SCORECOND
81.58 80.00
tb.dut.u_staterd.u_tlul_adapter.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt

SCORECOND
81.58 80.00
tb.dut.u_staterd.u_tlul_adapter.u_rspfifo.gen_normal_fifo.u_fifo_cnt

TotalCoveredPercent
Conditions201680.00
Logical201680.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       51
 SUB-EXPRESSION (wptr_o == 1'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       52
 SUB-EXPRESSION (rptr_o == 1'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       68
 EXPRESSION (full_o ? (1'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((1'(wptr_o) - 1'(rptr_o))) : (((1'(Depth) - 1'(rptr_o)) + 1'(wptr_o)))))
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((1'(wptr_o) - 1'(rptr_o))) : (((1'(Depth) - 1'(rptr_o)) + 1'(wptr_o))))
                 ----------------1---------------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

Cond Coverage for Module : prim_fifo_sync_cnt ( parameter Depth=10,Secure=0,PtrW=4,DepthW=4,WrapPtrW=5 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_msgfifo.u_msgfifo.gen_normal_fifo.u_fifo_cnt

TotalCoveredPercent
Conditions2020100.00
Logical2020100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 4'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       51
 SUB-EXPRESSION (wptr_o == 4'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 4'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       52
 SUB-EXPRESSION (rptr_o == 4'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT21,T22,T25

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       68
 EXPRESSION (full_o ? (4'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((4'(wptr_o) - 4'(rptr_o))) : (((4'(Depth) - 4'(rptr_o)) + 4'(wptr_o)))))
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT21,T22,T25

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((4'(wptr_o) - 4'(rptr_o))) : (((4'(Depth) - 4'(rptr_o)) + 4'(wptr_o))))
                 ----------------1---------------
-1-StatusTests
0CoveredT12,T13,T16
1CoveredT1,T2,T3

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------
-1-StatusTests
0CoveredT12,T13,T16
1CoveredT1,T2,T3

Branch Coverage for Module : prim_fifo_sync_cnt
Line No.TotalCoveredPercent
Branches 13 13 100.00
TERNARY 68 3 3 100.00
IF 113 5 5 100.00
IF 125 5 5 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 68 (full_o) ? -2-: 68 ((wptr_wrap_msb == rptr_wrap_msb)) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T12,T13,T16


LineNo. Expression -1-: 113 if ((!rst_ni)) -2-: 115 if (clr_i) -3-: 117 if (wptr_wrap_set) -4-: 119 if (incr_wptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T1,T2,T3
0 0 0 1 Covered T1,T2,T3
0 0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 125 if ((!rst_ni)) -2-: 127 if (clr_i) -3-: 129 if (rptr_wrap_set) -4-: 131 if (incr_rptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T1,T2,T3
0 0 0 1 Covered T1,T2,T3
0 0 0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
TOTAL222090.91
CONT_ASSIGN4111100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5200
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6811100.00
ALWAYS1137571.43
ALWAYS12555100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
41 1 1
42 1 1
46 1 1
47 1 1
51 1 1
52 unreachable
55 1 1
56 1 1
59 1 1
61 1 1
68 1 1
113 1 1
114 1 1
115 1 1
116 unreachable
117 1 1
118 0 1
119 1 1
120 0 1
MISSING_ELSE
125 1 1
126 1 1
127 1 1
128 unreachable
129 1 1
130 unreachable
131 1 1
132 unreachable
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt
TotalCoveredPercent
Conditions181266.67
Logical181266.67
Non-Logical00
Event00

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       51
 SUB-EXPRESSION (wptr_o == 1'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable

 LINE       52
 SUB-EXPRESSION (rptr_o == 1'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       68
 EXPRESSION (full_o ? (1'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((1'(wptr_o) - 1'(rptr_o))) : (((1'(Depth) - 1'(rptr_o)) + 1'(wptr_o)))))
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((1'(wptr_o) - 1'(rptr_o))) : (((1'(Depth) - 1'(rptr_o)) + 1'(wptr_o))))
                 ----------------1---------------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
Branches 9 5 55.56
TERNARY 68 3 1 33.33
IF 113 4 2 50.00
IF 125 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 68 (full_o) ? -2-: 68 ((wptr_wrap_msb == rptr_wrap_msb)) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Covered T1,T2,T3
0 0 Not Covered


LineNo. Expression -1-: 113 if ((!rst_ni)) -2-: 115 if (clr_i) -3-: 117 if (wptr_wrap_set) -4-: 119 if (incr_wptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Unreachable
0 0 1 - Not Covered
0 0 0 1 Not Covered
0 0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 125 if ((!rst_ni)) -2-: 127 if (clr_i) -3-: 129 if (rptr_wrap_set) -4-: 131 if (incr_rptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Unreachable
0 0 1 - Unreachable
0 0 0 1 Unreachable
0 0 0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_rspfifo.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
TOTAL222090.91
CONT_ASSIGN4111100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5100
CONT_ASSIGN5211100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6811100.00
ALWAYS11355100.00
ALWAYS1257571.43
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
41 1 1
42 1 1
46 1 1
47 1 1
51 unreachable
52 1 1
55 1 1
56 1 1
59 1 1
61 1 1
68 1 1
113 1 1
114 1 1
115 1 1
116 unreachable
117 1 1
118 unreachable
119 1 1
120 unreachable
MISSING_ELSE
125 1 1
126 1 1
127 1 1
128 unreachable
129 1 1
130 0 1
131 1 1
132 0 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_rspfifo.gen_normal_fifo.u_fifo_cnt
TotalCoveredPercent
Conditions181266.67
Logical181266.67
Non-Logical00
Event00

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable

 LINE       51
 SUB-EXPRESSION (wptr_o == 1'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       52
 SUB-EXPRESSION (rptr_o == 1'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       68
 EXPRESSION (full_o ? (1'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((1'(wptr_o) - 1'(rptr_o))) : (((1'(Depth) - 1'(rptr_o)) + 1'(wptr_o)))))
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((1'(wptr_o) - 1'(rptr_o))) : (((1'(Depth) - 1'(rptr_o)) + 1'(wptr_o))))
                 ----------------1---------------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_rspfifo.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
Branches 9 5 55.56
TERNARY 68 3 1 33.33
IF 113 2 2 100.00
IF 125 4 2 50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 68 (full_o) ? -2-: 68 ((wptr_wrap_msb == rptr_wrap_msb)) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Covered T1,T2,T3
0 0 Not Covered


LineNo. Expression -1-: 113 if ((!rst_ni)) -2-: 115 if (clr_i) -3-: 117 if (wptr_wrap_set) -4-: 119 if (incr_wptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Unreachable
0 0 1 - Unreachable
0 0 0 1 Unreachable
0 0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 125 if ((!rst_ni)) -2-: 127 if (clr_i) -3-: 129 if (rptr_wrap_set) -4-: 131 if (incr_rptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Unreachable
0 0 1 - Not Covered
0 0 0 1 Not Covered
0 0 0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_reqfifo.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
TOTAL252392.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6811100.00
ALWAYS1137685.71
ALWAYS1257685.71
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
41 1 1
42 1 1
46 1 1
47 1 1
51 1 1
52 1 1
55 1 1
56 1 1
59 1 1
61 1 1
68 1 1
113 1 1
114 1 1
115 1 1
116 unreachable
117 1 1
118 1 1
119 1 1
120 0 1
MISSING_ELSE
125 1 1
126 1 1
127 1 1
128 unreachable
129 1 1
130 1 1
131 1 1
132 0 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_reqfifo.gen_normal_fifo.u_fifo_cnt
TotalCoveredPercent
Conditions201680.00
Logical201680.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       51
 SUB-EXPRESSION (wptr_o == 1'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       52
 SUB-EXPRESSION (rptr_o == 1'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       68
 EXPRESSION (full_o ? (1'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((1'(wptr_o) - 1'(rptr_o))) : (((1'(Depth) - 1'(rptr_o)) + 1'(wptr_o)))))
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((1'(wptr_o) - 1'(rptr_o))) : (((1'(Depth) - 1'(rptr_o)) + 1'(wptr_o))))
                 ----------------1---------------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_reqfifo.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
Branches 11 8 72.73
TERNARY 68 3 2 66.67
IF 113 4 3 75.00
IF 125 4 3 75.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 68 (full_o) ? -2-: 68 ((wptr_wrap_msb == rptr_wrap_msb)) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Not Covered


LineNo. Expression -1-: 113 if ((!rst_ni)) -2-: 115 if (clr_i) -3-: 117 if (wptr_wrap_set) -4-: 119 if (incr_wptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Unreachable
0 0 1 - Covered T1,T2,T3
0 0 0 1 Not Covered
0 0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 125 if ((!rst_ni)) -2-: 127 if (clr_i) -3-: 129 if (rptr_wrap_set) -4-: 131 if (incr_rptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Unreachable
0 0 1 - Covered T1,T2,T3
0 0 0 1 Not Covered
0 0 0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_reqfifo.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
TOTAL252392.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6811100.00
ALWAYS1137685.71
ALWAYS1257685.71
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
41 1 1
42 1 1
46 1 1
47 1 1
51 1 1
52 1 1
55 1 1
56 1 1
59 1 1
61 1 1
68 1 1
113 1 1
114 1 1
115 1 1
116 unreachable
117 1 1
118 1 1
119 1 1
120 0 1
MISSING_ELSE
125 1 1
126 1 1
127 1 1
128 unreachable
129 1 1
130 1 1
131 1 1
132 0 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_reqfifo.gen_normal_fifo.u_fifo_cnt
TotalCoveredPercent
Conditions201680.00
Logical201680.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       51
 SUB-EXPRESSION (wptr_o == 1'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       52
 SUB-EXPRESSION (rptr_o == 1'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       68
 EXPRESSION (full_o ? (1'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((1'(wptr_o) - 1'(rptr_o))) : (((1'(Depth) - 1'(rptr_o)) + 1'(wptr_o)))))
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((1'(wptr_o) - 1'(rptr_o))) : (((1'(Depth) - 1'(rptr_o)) + 1'(wptr_o))))
                 ----------------1---------------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_reqfifo.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
Branches 11 8 72.73
TERNARY 68 3 2 66.67
IF 113 4 3 75.00
IF 125 4 3 75.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 68 (full_o) ? -2-: 68 ((wptr_wrap_msb == rptr_wrap_msb)) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Not Covered


LineNo. Expression -1-: 113 if ((!rst_ni)) -2-: 115 if (clr_i) -3-: 117 if (wptr_wrap_set) -4-: 119 if (incr_wptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Unreachable
0 0 1 - Covered T1,T2,T3
0 0 0 1 Not Covered
0 0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 125 if ((!rst_ni)) -2-: 127 if (clr_i) -3-: 129 if (rptr_wrap_set) -4-: 131 if (incr_rptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Unreachable
0 0 1 - Covered T1,T2,T3
0 0 0 1 Not Covered
0 0 0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
TOTAL252392.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6811100.00
ALWAYS1137685.71
ALWAYS1257685.71
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
41 1 1
42 1 1
46 1 1
47 1 1
51 1 1
52 1 1
55 1 1
56 1 1
59 1 1
61 1 1
68 1 1
113 1 1
114 1 1
115 1 1
116 unreachable
117 1 1
118 1 1
119 1 1
120 0 1
MISSING_ELSE
125 1 1
126 1 1
127 1 1
128 unreachable
129 1 1
130 1 1
131 1 1
132 0 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt
TotalCoveredPercent
Conditions201680.00
Logical201680.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       51
 SUB-EXPRESSION (wptr_o == 1'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       52
 SUB-EXPRESSION (rptr_o == 1'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       68
 EXPRESSION (full_o ? (1'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((1'(wptr_o) - 1'(rptr_o))) : (((1'(Depth) - 1'(rptr_o)) + 1'(wptr_o)))))
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((1'(wptr_o) - 1'(rptr_o))) : (((1'(Depth) - 1'(rptr_o)) + 1'(wptr_o))))
                 ----------------1---------------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
Branches 11 8 72.73
TERNARY 68 3 2 66.67
IF 113 4 3 75.00
IF 125 4 3 75.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 68 (full_o) ? -2-: 68 ((wptr_wrap_msb == rptr_wrap_msb)) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Not Covered


LineNo. Expression -1-: 113 if ((!rst_ni)) -2-: 115 if (clr_i) -3-: 117 if (wptr_wrap_set) -4-: 119 if (incr_wptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Unreachable
0 0 1 - Covered T1,T2,T3
0 0 0 1 Not Covered
0 0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 125 if ((!rst_ni)) -2-: 127 if (clr_i) -3-: 129 if (rptr_wrap_set) -4-: 131 if (incr_rptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Unreachable
0 0 1 - Covered T1,T2,T3
0 0 0 1 Not Covered
0 0 0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_rspfifo.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
TOTAL252392.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6811100.00
ALWAYS1137685.71
ALWAYS1257685.71
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
41 1 1
42 1 1
46 1 1
47 1 1
51 1 1
52 1 1
55 1 1
56 1 1
59 1 1
61 1 1
68 1 1
113 1 1
114 1 1
115 1 1
116 unreachable
117 1 1
118 1 1
119 1 1
120 0 1
MISSING_ELSE
125 1 1
126 1 1
127 1 1
128 unreachable
129 1 1
130 1 1
131 1 1
132 0 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_rspfifo.gen_normal_fifo.u_fifo_cnt
TotalCoveredPercent
Conditions201680.00
Logical201680.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       51
 SUB-EXPRESSION (wptr_o == 1'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       52
 SUB-EXPRESSION (rptr_o == 1'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT14,T15,T16

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       68
 EXPRESSION (full_o ? (1'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((1'(wptr_o) - 1'(rptr_o))) : (((1'(Depth) - 1'(rptr_o)) + 1'(wptr_o)))))
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT14,T15,T16

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((1'(wptr_o) - 1'(rptr_o))) : (((1'(Depth) - 1'(rptr_o)) + 1'(wptr_o))))
                 ----------------1---------------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_rspfifo.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
Branches 11 8 72.73
TERNARY 68 3 2 66.67
IF 113 4 3 75.00
IF 125 4 3 75.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 68 (full_o) ? -2-: 68 ((wptr_wrap_msb == rptr_wrap_msb)) ?

Branches:
-1--2-StatusTests
1 - Covered T14,T15,T16
0 1 Covered T1,T2,T3
0 0 Not Covered


LineNo. Expression -1-: 113 if ((!rst_ni)) -2-: 115 if (clr_i) -3-: 117 if (wptr_wrap_set) -4-: 119 if (incr_wptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Unreachable
0 0 1 - Covered T1,T2,T3
0 0 0 1 Not Covered
0 0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 125 if ((!rst_ni)) -2-: 127 if (clr_i) -3-: 129 if (rptr_wrap_set) -4-: 131 if (incr_rptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Unreachable
0 0 1 - Covered T1,T2,T3
0 0 0 1 Not Covered
0 0 0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_msgfifo.u_msgfifo.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
TOTAL2727100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6811100.00
ALWAYS11388100.00
ALWAYS12588100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
41 1 1
42 1 1
46 1 1
47 1 1
51 1 1
52 1 1
55 1 1
56 1 1
59 1 1
61 1 1
68 1 1
113 1 1
114 1 1
115 1 1
116 1 1
117 1 1
118 1 1
119 1 1
120 1 1
MISSING_ELSE
125 1 1
126 1 1
127 1 1
128 1 1
129 1 1
130 1 1
131 1 1
132 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_msgfifo.u_msgfifo.gen_normal_fifo.u_fifo_cnt
TotalCoveredPercent
Conditions2020100.00
Logical2020100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 4'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       51
 SUB-EXPRESSION (wptr_o == 4'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 4'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       52
 SUB-EXPRESSION (rptr_o == 4'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT21,T22,T25

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       68
 EXPRESSION (full_o ? (4'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((4'(wptr_o) - 4'(rptr_o))) : (((4'(Depth) - 4'(rptr_o)) + 4'(wptr_o)))))
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT21,T22,T25

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((4'(wptr_o) - 4'(rptr_o))) : (((4'(Depth) - 4'(rptr_o)) + 4'(wptr_o))))
                 ----------------1---------------
-1-StatusTests
0CoveredT12,T13,T16
1CoveredT1,T2,T3

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------
-1-StatusTests
0CoveredT12,T13,T16
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_msgfifo.u_msgfifo.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
Branches 13 13 100.00
TERNARY 68 3 3 100.00
IF 113 5 5 100.00
IF 125 5 5 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 68 (full_o) ? -2-: 68 ((wptr_wrap_msb == rptr_wrap_msb)) ?

Branches:
-1--2-StatusTests
1 - Covered T21,T22,T25
0 1 Covered T1,T2,T3
0 0 Covered T12,T13,T16


LineNo. Expression -1-: 113 if ((!rst_ni)) -2-: 115 if (clr_i) -3-: 117 if (wptr_wrap_set) -4-: 119 if (incr_wptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T1,T2,T3
0 0 0 1 Covered T1,T2,T3
0 0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 125 if ((!rst_ni)) -2-: 127 if (clr_i) -3-: 129 if (rptr_wrap_set) -4-: 131 if (incr_rptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T1,T2,T3
0 0 0 1 Covered T1,T2,T3
0 0 0 0 Covered T1,T2,T3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%