Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	312572	0	0
entropy_period_rd_A	2147483647	2322	0	0
intr_enable_rd_A	2147483647	3178	0	0
prefix_0_rd_A	2147483647	2090	0	0
prefix_10_rd_A	2147483647	2057	0	0
prefix_1_rd_A	2147483647	2137	0	0
prefix_2_rd_A	2147483647	1999	0	0
prefix_3_rd_A	2147483647	2071	0	0
prefix_4_rd_A	2147483647	2088	0	0
prefix_5_rd_A	2147483647	2197	0	0
prefix_6_rd_A	2147483647	2159	0	0
prefix_7_rd_A	2147483647	2156	0	0
prefix_8_rd_A	2147483647	2095	0	0
prefix_9_rd_A	2147483647	2092	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	312572	0	0
T19	95112	0	0	0
T24	570854	0	0	0
T28	367134	0	0	0
T31	740984	99114	0	0
T37	4317	0	0	0
T54	0	54199	0	0
T55	0	28584	0	0
T71	5818	0	0	0
T74	18801	0	0	0
T75	6155	0	0	0
T92	0	32872	0	0
T93	0	22928	0	0
T111	0	4	0	0
T117	0	30848	0	0
T118	0	24667	0	0
T119	0	15779	0	0
T120	0	4	0	0
T121	428864	0	0	0
T122	977319	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2322	0	0
T92	412791	60	0	0
T93	0	100	0	0
T95	0	43	0	0
T96	0	26	0	0
T113	0	124	0	0
T120	0	22	0	0
T130	0	4	0	0
T131	0	32	0	0
T132	0	39	0	0
T133	0	89	0	0
T134	803616	0	0	0
T135	536415	0	0	0
T136	334899	0	0	0
T137	133644	0	0	0
T138	152986	0	0	0
T139	48811	0	0	0
T140	509390	0	0	0
T141	245626	0	0	0
T142	178277	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3178	0	0
T92	412791	79	0	0
T93	0	47	0	0
T95	0	32	0	0
T96	0	40	0	0
T113	0	157	0	0
T116	0	22	0	0
T120	0	20	0	0
T130	0	6	0	0
T131	0	46	0	0
T132	0	75	0	0
T134	803616	0	0	0
T135	536415	0	0	0
T136	334899	0	0	0
T137	133644	0	0	0
T138	152986	0	0	0
T139	48811	0	0	0
T140	509390	0	0	0
T141	245626	0	0	0
T142	178277	0	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2090	0	0
T92	412791	74	0	0
T93	0	69	0	0
T95	0	18	0	0
T96	0	20	0	0
T113	0	94	0	0
T120	0	14	0	0
T130	0	10	0	0
T131	0	4	0	0
T133	0	74	0	0
T134	803616	0	0	0
T135	536415	0	0	0
T136	334899	0	0	0
T137	133644	0	0	0
T138	152986	0	0	0
T139	48811	0	0	0
T140	509390	0	0	0
T141	245626	0	0	0
T142	178277	0	0	0
T143	0	427	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2057	0	0
T92	412791	52	0	0
T93	0	68	0	0
T95	0	56	0	0
T96	0	38	0	0
T113	0	82	0	0
T120	0	5	0	0
T130	0	11	0	0
T131	0	29	0	0
T132	0	20	0	0
T133	0	57	0	0
T134	803616	0	0	0
T135	536415	0	0	0
T136	334899	0	0	0
T137	133644	0	0	0
T138	152986	0	0	0
T139	48811	0	0	0
T140	509390	0	0	0
T141	245626	0	0	0
T142	178277	0	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2137	0	0
T92	412791	72	0	0
T93	0	86	0	0
T95	0	42	0	0
T96	0	38	0	0
T113	0	64	0	0
T120	0	14	0	0
T130	0	9	0	0
T131	0	38	0	0
T132	0	33	0	0
T133	0	80	0	0
T134	803616	0	0	0
T135	536415	0	0	0
T136	334899	0	0	0
T137	133644	0	0	0
T138	152986	0	0	0
T139	48811	0	0	0
T140	509390	0	0	0
T141	245626	0	0	0
T142	178277	0	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1999	0	0
T92	412791	66	0	0
T93	0	44	0	0
T95	0	44	0	0
T96	0	18	0	0
T113	0	65	0	0
T120	0	18	0	0
T130	0	11	0	0
T131	0	40	0	0
T132	0	25	0	0
T133	0	83	0	0
T134	803616	0	0	0
T135	536415	0	0	0
T136	334899	0	0	0
T137	133644	0	0	0
T138	152986	0	0	0
T139	48811	0	0	0
T140	509390	0	0	0
T141	245626	0	0	0
T142	178277	0	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2071	0	0
T92	412791	89	0	0
T93	0	109	0	0
T95	0	24	0	0
T96	0	30	0	0
T113	0	66	0	0
T120	0	7	0	0
T131	0	14	0	0
T132	0	21	0	0
T133	0	94	0	0
T134	803616	0	0	0
T135	536415	0	0	0
T136	334899	0	0	0
T137	133644	0	0	0
T138	152986	0	0	0
T139	48811	0	0	0
T140	509390	0	0	0
T141	245626	0	0	0
T142	178277	0	0	0
T143	0	413	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2088	0	0
T92	412791	69	0	0
T93	0	76	0	0
T95	0	29	0	0
T96	0	32	0	0
T113	0	80	0	0
T120	0	18	0	0
T130	0	3	0	0
T131	0	20	0	0
T132	0	17	0	0
T133	0	92	0	0
T134	803616	0	0	0
T135	536415	0	0	0
T136	334899	0	0	0
T137	133644	0	0	0
T138	152986	0	0	0
T139	48811	0	0	0
T140	509390	0	0	0
T141	245626	0	0	0
T142	178277	0	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2197	0	0
T92	412791	110	0	0
T93	0	86	0	0
T95	0	24	0	0
T96	0	24	0	0
T113	0	83	0	0
T120	0	16	0	0
T130	0	1	0	0
T131	0	23	0	0
T132	0	42	0	0
T133	0	114	0	0
T134	803616	0	0	0
T135	536415	0	0	0
T136	334899	0	0	0
T137	133644	0	0	0
T138	152986	0	0	0
T139	48811	0	0	0
T140	509390	0	0	0
T141	245626	0	0	0
T142	178277	0	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2159	0	0
T92	412791	91	0	0
T93	0	61	0	0
T95	0	31	0	0
T96	0	32	0	0
T113	0	67	0	0
T120	0	14	0	0
T131	0	25	0	0
T132	0	23	0	0
T133	0	82	0	0
T134	803616	0	0	0
T135	536415	0	0	0
T136	334899	0	0	0
T137	133644	0	0	0
T138	152986	0	0	0
T139	48811	0	0	0
T140	509390	0	0	0
T141	245626	0	0	0
T142	178277	0	0	0
T143	0	402	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2156	0	0
T92	412791	77	0	0
T93	0	70	0	0
T95	0	37	0	0
T96	0	39	0	0
T113	0	86	0	0
T120	0	15	0	0
T130	0	4	0	0
T131	0	13	0	0
T133	0	81	0	0
T134	803616	0	0	0
T135	536415	0	0	0
T136	334899	0	0	0
T137	133644	0	0	0
T138	152986	0	0	0
T139	48811	0	0	0
T140	509390	0	0	0
T141	245626	0	0	0
T142	178277	0	0	0
T143	0	408	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2095	0	0
T92	412791	94	0	0
T93	0	69	0	0
T95	0	20	0	0
T96	0	20	0	0
T113	0	75	0	0
T120	0	12	0	0
T130	0	8	0	0
T131	0	29	0	0
T132	0	7	0	0
T133	0	89	0	0
T134	803616	0	0	0
T135	536415	0	0	0
T136	334899	0	0	0
T137	133644	0	0	0
T138	152986	0	0	0
T139	48811	0	0	0
T140	509390	0	0	0
T141	245626	0	0	0
T142	178277	0	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2092	0	0
T92	412791	75	0	0
T93	0	79	0	0
T95	0	44	0	0
T96	0	26	0	0
T113	0	70	0	0
T120	0	8	0	0
T130	0	10	0	0
T131	0	8	0	0
T132	0	20	0	0
T133	0	69	0	0
T134	803616	0	0	0
T135	536415	0	0	0
T136	334899	0	0	0
T137	133644	0	0	0
T138	152986	0	0	0
T139	48811	0	0	0
T140	509390	0	0	0
T141	245626	0	0	0
T142	178277	0	0	0