Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	258922871	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

205031812

1

T1

98101

T2

74341

T3

184208

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	244962309	1			T1	104281		T2	95435		T3	232439
values[0x0]	105164363	1			T1	22856		T2	40130		T3	105272
values[0x1]	113828011	1			T1	24377		T2	44231		T3	113045

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	201710969	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

262243714

1

T1

110170

T2

97813

T3

241877

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1396976	1			T1	536		T2	706		T3	1834
valid_sources[0x01]	1400284	1			T1	563		T2	713		T3	1822
valid_sources[0x02]	2361311	1			T1	574		T2	671		T3	1843
valid_sources[0x03]	1405916	1			T1	515		T2	737		T3	1749
valid_sources[0x04]	1541915	1			T1	627		T2	731		T3	1813
valid_sources[0x05]	2249081	1			T1	598		T2	683		T3	1832
valid_sources[0x06]	2266888	1			T1	644		T2	743		T3	1712
valid_sources[0x07]	1404624	1			T1	592		T2	725		T3	1792
valid_sources[0x08]	1431052	1			T1	547		T2	691		T3	1759
valid_sources[0x09]	3476937	1			T1	550		T2	670		T3	1869
valid_sources[0x0a]	1402091	1			T1	582		T2	662		T3	1696
valid_sources[0x0b]	1527906	1			T1	547		T2	705		T3	1720
valid_sources[0x0c]	1532687	1			T1	599		T2	734		T3	1797
valid_sources[0x0d]	2315113	1			T1	521		T2	687		T3	1772
valid_sources[0x0e]	1408131	1			T1	567		T2	725		T3	1780
valid_sources[0x0f]	1869874	1			T1	625		T2	724		T3	1746
valid_sources[0x10]	3438232	1			T1	582		T2	732		T3	1769
valid_sources[0x11]	1399666	1			T1	637		T2	710		T3	1784
valid_sources[0x12]	1571064	1			T1	655		T2	734		T3	1779
valid_sources[0x13]	1402257	1			T1	641		T2	735		T3	1654
valid_sources[0x14]	3828824	1			T1	610		T2	807		T3	1781
valid_sources[0x15]	1408141	1			T1	530		T2	719		T3	1861
valid_sources[0x16]	1402814	1			T1	557		T2	741		T3	1710
valid_sources[0x17]	2060679	1			T1	539		T2	790		T3	1776
valid_sources[0x18]	1462184	1			T1	554		T2	734		T3	1714
valid_sources[0x19]	1407275	1			T1	593		T2	700		T3	1721
valid_sources[0x1a]	1397393	1			T1	538		T2	667		T3	1846
valid_sources[0x1b]	1411975	1			T1	529		T2	675		T3	1777
valid_sources[0x1c]	3553506	1			T1	637		T2	624		T3	1815
valid_sources[0x1d]	2076681	1			T1	521		T2	676		T3	1728
valid_sources[0x1e]	3644476	1			T1	635		T2	752		T3	1772
valid_sources[0x1f]	1462071	1			T1	612		T2	679		T3	1673
valid_sources[0x20]	1464627	1			T1	602		T2	642		T3	1836
valid_sources[0x21]	1407937	1			T1	619		T2	697		T3	1873
valid_sources[0x22]	1404685	1			T1	583		T2	725		T3	1814
valid_sources[0x23]	1397541	1			T1	654		T2	748		T3	1742
valid_sources[0x24]	2274005	1			T1	622		T2	681		T3	1764
valid_sources[0x25]	1404088	1			T1	630		T2	655		T3	1660
valid_sources[0x26]	1394997	1			T1	552		T2	739		T3	1712
valid_sources[0x27]	2257952	1			T1	575		T2	748		T3	1804
valid_sources[0x28]	4304143	1			T1	606		T2	610		T3	1787
valid_sources[0x29]	2453916	1			T1	578		T2	697		T3	1753
valid_sources[0x2a]	1412734	1			T1	611		T2	689		T3	1774
valid_sources[0x2b]	2064990	1			T1	583		T2	623		T3	1776
valid_sources[0x2c]	2294401	1			T1	591		T2	695		T3	1780
valid_sources[0x2d]	1407060	1			T1	606		T2	719		T3	1734
valid_sources[0x2e]	3463011	1			T1	511		T2	633		T3	1765
valid_sources[0x2f]	1437917	1			T1	589		T2	720		T3	1745
valid_sources[0x30]	1408424	1			T1	584		T2	692		T3	1801
valid_sources[0x31]	1404900	1			T1	577		T2	710		T3	1758
valid_sources[0x32]	1408285	1			T1	613		T2	737		T3	1723
valid_sources[0x33]	1402416	1			T1	596		T2	733		T3	1680
valid_sources[0x34]	1399112	1			T1	598		T2	710		T3	1758
valid_sources[0x35]	1404432	1			T1	634		T2	719		T3	1746
valid_sources[0x36]	1857163	1			T1	561		T2	716		T3	1737
valid_sources[0x37]	2279937	1			T1	598		T2	707		T3	1791
valid_sources[0x38]	1407413	1			T1	577		T2	617		T3	1737
valid_sources[0x39]	1403749	1			T1	601		T2	674		T3	1746
valid_sources[0x3a]	1410760	1			T1	541		T2	635		T3	1729
valid_sources[0x3b]	2219504	1			T1	681		T2	771		T3	1797
valid_sources[0x3c]	1511519	1			T1	589		T2	737		T3	1687
valid_sources[0x3d]	1398966	1			T1	593		T2	650		T3	1740
valid_sources[0x3e]	1630295	1			T1	650		T2	655		T3	1813
valid_sources[0x3f]	1398811	1			T1	585		T2	686		T3	1758
valid_sources[0x40]	1404275	1			T1	665		T2	624		T3	1755
valid_sources[0x41]	2321673	1			T1	633		T2	730		T3	1792
valid_sources[0x42]	1402870	1			T1	528		T2	727		T3	1740
valid_sources[0x43]	3165594	1			T1	583		T2	664		T3	1781
valid_sources[0x44]	1404792	1			T1	553		T2	716		T3	1762
valid_sources[0x45]	1399249	1			T1	635		T2	705		T3	1810
valid_sources[0x46]	1416125	1			T1	570		T2	696		T3	1722
valid_sources[0x47]	1410440	1			T1	589		T2	666		T3	1760
valid_sources[0x48]	1396334	1			T1	604		T2	730		T3	1707
valid_sources[0x49]	3831255	1			T1	586		T2	670		T3	1738
valid_sources[0x4a]	1399879	1			T1	596		T2	713		T3	1757
valid_sources[0x4b]	1409087	1			T1	578		T2	623		T3	1703
valid_sources[0x4c]	1404521	1			T1	623		T2	676		T3	1748
valid_sources[0x4d]	4576938	1			T1	578		T2	716		T3	1818
valid_sources[0x4e]	2149043	1			T1	599		T2	725		T3	1829
valid_sources[0x4f]	1404712	1			T1	604		T2	782		T3	1761
valid_sources[0x50]	2089773	1			T1	496		T2	618		T3	1742
valid_sources[0x51]	1567621	1			T1	557		T2	721		T3	1716
valid_sources[0x52]	1406400	1			T1	592		T2	643		T3	1716
valid_sources[0x53]	1404056	1			T1	566		T2	632		T3	1853
valid_sources[0x54]	1422098	1			T1	618		T2	724		T3	1794
valid_sources[0x55]	3841001	1			T1	586		T2	683		T3	1686
valid_sources[0x56]	1544567	1			T1	556		T2	696		T3	1747
valid_sources[0x57]	1433167	1			T1	559		T2	733		T3	1728
valid_sources[0x58]	1396642	1			T1	687		T2	681		T3	1804
valid_sources[0x59]	4828855	1			T1	606		T2	681		T3	1832
valid_sources[0x5a]	1405890	1			T1	554		T2	685		T3	1797
valid_sources[0x5b]	1593878	1			T1	642		T2	657		T3	1758
valid_sources[0x5c]	2100718	1			T1	592		T2	692		T3	1746
valid_sources[0x5d]	1404635	1			T1	539		T2	633		T3	1741
valid_sources[0x5e]	1407068	1			T1	538		T2	689		T3	1802
valid_sources[0x5f]	1525824	1			T1	557		T2	693		T3	1697
valid_sources[0x60]	1403692	1			T1	652		T2	714		T3	1744
valid_sources[0x61]	1420799	1			T1	571		T2	788		T3	1824
valid_sources[0x62]	2320541	1			T1	586		T2	704		T3	1721
valid_sources[0x63]	1395829	1			T1	614		T2	712		T3	1793
valid_sources[0x64]	1392102	1			T1	598		T2	720		T3	1809
valid_sources[0x65]	3472513	1			T1	559		T2	764		T3	1795
valid_sources[0x66]	1401960	1			T1	618		T2	736		T3	1710
valid_sources[0x67]	1396405	1			T1	546		T2	692		T3	1761
valid_sources[0x68]	1773289	1			T1	627		T2	707		T3	1801
valid_sources[0x69]	1396957	1			T1	592		T2	699		T3	1728
valid_sources[0x6a]	1642187	1			T1	512		T2	614		T3	1761
valid_sources[0x6b]	1407427	1			T1	628		T2	639		T3	1698
valid_sources[0x6c]	1427683	1			T1	641		T2	767		T3	1780
valid_sources[0x6d]	1540965	1			T1	609		T2	727		T3	1845
valid_sources[0x6e]	2061981	1			T1	651		T2	729		T3	1720
valid_sources[0x6f]	2053432	1			T1	522		T2	691		T3	1715
valid_sources[0x70]	1597789	1			T1	643		T2	711		T3	1787
valid_sources[0x71]	1394993	1			T1	577		T2	730		T3	1689
valid_sources[0x72]	1407894	1			T1	522		T2	771		T3	1725
valid_sources[0x73]	2083096	1			T1	574		T2	691		T3	1771
valid_sources[0x74]	1406119	1			T1	612		T2	688		T3	1756
valid_sources[0x75]	2121353	1			T1	588		T2	702		T3	1694
valid_sources[0x76]	1412941	1			T1	587		T2	670		T3	1715
valid_sources[0x77]	1407045	1			T1	552		T2	741		T3	1792
valid_sources[0x78]	1406236	1			T1	578		T2	738		T3	1741
valid_sources[0x79]	1420064	1			T1	568		T2	685		T3	1737
valid_sources[0x7a]	1415049	1			T1	591		T2	720		T3	1771
valid_sources[0x7b]	1402340	1			T1	610		T2	690		T3	1796
valid_sources[0x7c]	2274051	1			T1	624		T2	737		T3	1749
valid_sources[0x7d]	3414917	1			T1	642		T2	664		T3	1739
valid_sources[0x7e]	1400272	1			T1	602		T2	722		T3	1716
valid_sources[0x7f]	1401073	1			T1	582		T2	629		T3	1715
valid_sources[0x80]	1395657	1			T1	489		T2	718		T3	1724

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

89676830

1

T1

71556

T2

32862

T3

70489

values[0x0]

all_enables

biggest_size

62036948

1

T1

14309

T2

22399

T3

61383

values[0x1]

all_enables

biggest_size

53318034

1

T1

12236

T2

19080

T3

52336