Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

262431928

1

T1

53413

T2

105455

T3

266548

full_word

205254668

1

T1

98101

T2

74341

T3

184208

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	467686286	1			T1	151514		T2	179796		T3	450756
auto[TlIntgErrCmd]	112	1			T122	8		T123	7		T124	6
auto[TlIntgErrData]	95	1			T122	5		T123	7		T124	4
auto[TlIntgErrBoth]	103	1			T122	7		T123	6		T124	10

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

245652426

1

T1

104281

T2

95435

T3

232439

auto[1]

222034170

1

T1

47233

T2

84361

T3

218317

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	155919495	1			T1	32725		T2	62573		T3	161950
auto[TlIntgErrNone]	partial	auto[1]	106512142	1			T1	20688		T2	42882		T3	104598
auto[TlIntgErrNone]	full_word	auto[0]	89732784	1			T1	71556		T2	32862		T3	70489
auto[TlIntgErrNone]	full_word	auto[1]	115521865	1			T1	26545		T2	41479		T3	113719
auto[TlIntgErrCmd]	partial	auto[0]	58	1			T122	2		T123	4		T124	6
auto[TlIntgErrCmd]	partial	auto[1]	46	1			T122	6		T123	2		T170	1
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T123	1		T171	1		T173	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T174	1		T175	1		T176	1
auto[TlIntgErrData]	partial	auto[0]	39	1			T122	1		T123	3		T124	2
auto[TlIntgErrData]	partial	auto[1]	49	1			T122	4		T123	3		T124	2
auto[TlIntgErrData]	full_word	auto[0]	5	1			T123	1		T171	1		T177	1
auto[TlIntgErrData]	full_word	auto[1]	2	1			T170	1		T171	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	39	1			T122	1		T123	1		T124	4
auto[TlIntgErrBoth]	partial	auto[1]	60	1			T122	5		T123	5		T124	5
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T124	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T122	1		T174	1		T178	1