Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	828463	0	0
entropy_period_rd_A	2147483647	1471	0	0
intr_enable_rd_A	2147483647	1943	0	0
prefix_0_rd_A	2147483647	1185	0	0
prefix_10_rd_A	2147483647	993	0	0
prefix_1_rd_A	2147483647	1071	0	0
prefix_2_rd_A	2147483647	1069	0	0
prefix_3_rd_A	2147483647	1220	0	0
prefix_4_rd_A	2147483647	1232	0	0
prefix_5_rd_A	2147483647	1155	0	0
prefix_6_rd_A	2147483647	1083	0	0
prefix_7_rd_A	2147483647	1197	0	0
prefix_8_rd_A	2147483647	1135	0	0
prefix_9_rd_A	2147483647	1125	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	828463	0	0
T24	281858	44227	0	0
T25	445397	0	0	0
T33	0	95857	0	0
T35	0	97304	0	0
T42	754001	0	0	0
T51	0	72055	0	0
T52	0	40031	0	0
T60	177319	0	0	0
T81	925532	0	0	0
T82	117998	0	0	0
T83	147120	0	0	0
T84	869857	0	0	0
T85	87300	0	0	0
T86	504515	0	0	0
T90	0	38941	0	0
T95	0	11535	0	0
T128	0	59889	0	0
T129	0	129387	0	0
T130	0	83062	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1471	0	0
T95	147281	37	0	0
T96	0	93	0	0
T101	0	31	0	0
T122	0	132	0	0
T139	0	6	0	0
T140	0	13	0	0
T141	0	43	0	0
T142	0	8	0	0
T143	0	76	0	0
T144	0	15	0	0
T145	6328	0	0	0
T146	433139	0	0	0
T147	61280	0	0	0
T148	133299	0	0	0
T149	145297	0	0	0
T150	6122	0	0	0
T151	108687	0	0	0
T152	144999	0	0	0
T153	36240	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1943	0	0
T95	147281	37	0	0
T96	0	93	0	0
T101	0	61	0	0
T122	0	235	0	0
T127	0	18	0	0
T139	0	17	0	0
T140	0	8	0	0
T141	0	19	0	0
T142	0	5	0	0
T145	6328	0	0	0
T146	433139	0	0	0
T147	61280	0	0	0
T148	133299	0	0	0
T149	145297	0	0	0
T150	6122	0	0	0
T151	108687	0	0	0
T152	144999	0	0	0
T153	36240	0	0	0
T154	0	16	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1185	0	0
T95	147281	36	0	0
T96	0	78	0	0
T101	0	21	0	0
T122	0	66	0	0
T139	0	15	0	0
T140	0	6	0	0
T141	0	39	0	0
T142	0	8	0	0
T143	0	64	0	0
T144	0	6	0	0
T145	6328	0	0	0
T146	433139	0	0	0
T147	61280	0	0	0
T148	133299	0	0	0
T149	145297	0	0	0
T150	6122	0	0	0
T151	108687	0	0	0
T152	144999	0	0	0
T153	36240	0	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	993	0	0
T95	147281	4	0	0
T96	0	65	0	0
T101	0	30	0	0
T122	0	66	0	0
T139	0	21	0	0
T140	0	5	0	0
T141	0	3	0	0
T142	0	5	0	0
T143	0	54	0	0
T145	6328	0	0	0
T146	433139	0	0	0
T147	61280	0	0	0
T148	133299	0	0	0
T149	145297	0	0	0
T150	6122	0	0	0
T151	108687	0	0	0
T152	144999	0	0	0
T153	36240	0	0	0
T155	0	5	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1071	0	0
T95	147281	7	0	0
T96	0	128	0	0
T101	0	28	0	0
T122	0	72	0	0
T139	0	2	0	0
T140	0	10	0	0
T141	0	24	0	0
T142	0	2	0	0
T143	0	38	0	0
T144	0	6	0	0
T145	6328	0	0	0
T146	433139	0	0	0
T147	61280	0	0	0
T148	133299	0	0	0
T149	145297	0	0	0
T150	6122	0	0	0
T151	108687	0	0	0
T152	144999	0	0	0
T153	36240	0	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1069	0	0
T95	147281	14	0	0
T96	0	72	0	0
T101	0	28	0	0
T122	0	70	0	0
T139	0	6	0	0
T140	0	10	0	0
T141	0	49	0	0
T142	0	9	0	0
T143	0	34	0	0
T144	0	8	0	0
T145	6328	0	0	0
T146	433139	0	0	0
T147	61280	0	0	0
T148	133299	0	0	0
T149	145297	0	0	0
T150	6122	0	0	0
T151	108687	0	0	0
T152	144999	0	0	0
T153	36240	0	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1220	0	0
T95	147281	8	0	0
T96	0	130	0	0
T101	0	31	0	0
T122	0	94	0	0
T139	0	15	0	0
T140	0	9	0	0
T141	0	22	0	0
T142	0	8	0	0
T143	0	42	0	0
T144	0	11	0	0
T145	6328	0	0	0
T146	433139	0	0	0
T147	61280	0	0	0
T148	133299	0	0	0
T149	145297	0	0	0
T150	6122	0	0	0
T151	108687	0	0	0
T152	144999	0	0	0
T153	36240	0	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1232	0	0
T95	147281	36	0	0
T96	0	81	0	0
T101	0	46	0	0
T122	0	69	0	0
T139	0	9	0	0
T140	0	5	0	0
T141	0	48	0	0
T142	0	7	0	0
T143	0	52	0	0
T145	6328	0	0	0
T146	433139	0	0	0
T147	61280	0	0	0
T148	133299	0	0	0
T149	145297	0	0	0
T150	6122	0	0	0
T151	108687	0	0	0
T152	144999	0	0	0
T153	36240	0	0	0
T155	0	3	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1155	0	0
T95	147281	8	0	0
T96	0	119	0	0
T101	0	31	0	0
T122	0	95	0	0
T139	0	17	0	0
T140	0	13	0	0
T141	0	38	0	0
T142	0	7	0	0
T143	0	57	0	0
T145	6328	0	0	0
T146	433139	0	0	0
T147	61280	0	0	0
T148	133299	0	0	0
T149	145297	0	0	0
T150	6122	0	0	0
T151	108687	0	0	0
T152	144999	0	0	0
T153	36240	0	0	0
T155	0	4	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1083	0	0
T95	147281	57	0	0
T96	0	55	0	0
T101	0	21	0	0
T122	0	75	0	0
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T152	144999	0	0	0
T153	36240	0	0	0
T156	0	3	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1197	0	0
T95	147281	32	0	0
T96	0	114	0	0
T101	0	16	0	0
T122	0	82	0	0
T139	0	14	0	0
T140	0	3	0	0
T141	0	24	0	0
T142	0	12	0	0
T143	0	57	0	0
T144	0	11	0	0
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T150	6122	0	0	0
T151	108687	0	0	0
T152	144999	0	0	0
T153	36240	0	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1135	0	0
T95	147281	15	0	0
T96	0	114	0	0
T101	0	24	0	0
T122	0	88	0	0
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T152	144999	0	0	0
T153	36240	0	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1125	0	0
T95	147281	22	0	0
T96	0	86	0	0
T101	0	11	0	0
T122	0	65	0	0
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T155	0	4	0	0