Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	252969077	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

199323794

1

T1

887436

T2

1395

T3

1395

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	238941273	1			T1	110290		T2	1127		T3	1163
values[0x0]	102521209	1			T1	448228		T2	477		T3	544
values[0x1]	110830389	1			T1	483241		T2	560		T3	532

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	197239862	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

255053009

1

T1

113915

T2

1584

T3

1595

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1364542	1			T1	7944		T2	7		T3	4
valid_sources[0x01]	1357286	1			T1	7786		T2	14		T3	8
valid_sources[0x02]	1362198	1			T1	7917		T2	13		T3	6
valid_sources[0x03]	1355973	1			T1	8058		T2	3		T3	13
valid_sources[0x04]	1454624	1			T1	8032		T2	18		T3	8
valid_sources[0x05]	2238423	1			T1	7823		T2	13		T3	4
valid_sources[0x06]	1365279	1			T1	7991		T2	6		T3	10
valid_sources[0x07]	3432972	1			T1	7933		T2	8		T3	9
valid_sources[0x08]	1354283	1			T1	7853		T2	7		T3	11
valid_sources[0x09]	1364193	1			T1	7940		T2	11		T3	14
valid_sources[0x0a]	1512612	1			T1	7846		T2	14		T3	7
valid_sources[0x0b]	1362119	1			T1	7913		T2	9		T3	10
valid_sources[0x0c]	1359807	1			T1	7889		T2	6		T3	7
valid_sources[0x0d]	1821622	1			T1	8121		T2	10		T3	7
valid_sources[0x0e]	1364181	1			T1	8023		T2	7		T3	9
valid_sources[0x0f]	2150634	1			T1	7987		T2	9		T3	5
valid_sources[0x10]	2311594	1			T1	7712		T2	10		T3	8
valid_sources[0x11]	1363423	1			T1	7900		T2	7		T3	9
valid_sources[0x12]	1364350	1			T1	7748		T2	8		T3	12
valid_sources[0x13]	3797121	1			T1	7835		T3	11		T13	247
valid_sources[0x14]	1364083	1			T1	7911		T2	14		T3	9
valid_sources[0x15]	1365142	1			T1	7965		T2	18		T3	5
valid_sources[0x16]	1382240	1			T1	8071		T2	9		T3	5
valid_sources[0x17]	1824089	1			T1	7924		T2	6		T3	9
valid_sources[0x18]	1363814	1			T1	7986		T2	4		T3	9
valid_sources[0x19]	1390136	1			T1	8039		T2	5		T3	7
valid_sources[0x1a]	1355189	1			T1	8169		T2	14		T3	7
valid_sources[0x1b]	2008642	1			T1	7973		T2	3		T3	6
valid_sources[0x1c]	1370202	1			T1	8025		T2	4		T3	8
valid_sources[0x1d]	1446362	1			T1	7843		T2	8		T3	14
valid_sources[0x1e]	1454936	1			T1	7789		T2	5		T3	6
valid_sources[0x1f]	2275981	1			T1	7857		T2	20		T3	9
valid_sources[0x20]	1413581	1			T1	8107		T2	9		T3	14
valid_sources[0x21]	1359226	1			T1	8153		T2	13		T3	13
valid_sources[0x22]	1491611	1			T1	8087		T2	1		T3	7
valid_sources[0x23]	3795621	1			T1	7887		T2	6		T3	11
valid_sources[0x24]	1350356	1			T1	7910		T2	5		T3	12
valid_sources[0x25]	1353347	1			T1	7835		T2	7		T3	11
valid_sources[0x26]	1508981	1			T1	8067		T2	19		T3	12
valid_sources[0x27]	1358841	1			T1	7948		T2	7		T3	9
valid_sources[0x28]	1357901	1			T1	7986		T2	16		T3	9
valid_sources[0x29]	1365493	1			T1	7969		T2	12		T3	6
valid_sources[0x2a]	1443605	1			T1	8023		T2	17		T3	8
valid_sources[0x2b]	1374628	1			T1	8032		T2	4		T3	6
valid_sources[0x2c]	1360170	1			T1	7874		T2	13		T3	14
valid_sources[0x2d]	1365206	1			T1	7803		T2	9		T3	11
valid_sources[0x2e]	1399239	1			T1	7979		T2	10		T3	8
valid_sources[0x2f]	1509787	1			T1	7904		T2	3		T3	8
valid_sources[0x30]	1505510	1			T1	7898		T2	22		T3	12
valid_sources[0x31]	1362606	1			T1	7997		T2	6		T3	13
valid_sources[0x32]	1363391	1			T1	7979		T2	3		T3	5
valid_sources[0x33]	2081702	1			T1	7871		T2	6		T3	7
valid_sources[0x34]	1357144	1			T1	8016		T2	5		T3	7
valid_sources[0x35]	2692928	1			T1	8045		T2	4		T3	13
valid_sources[0x36]	3385872	1			T1	8137		T2	11		T3	10
valid_sources[0x37]	1365202	1			T1	7826		T2	6		T3	8
valid_sources[0x38]	1362548	1			T1	7958		T2	7		T3	15
valid_sources[0x39]	2230941	1			T1	7971		T2	8		T3	6
valid_sources[0x3a]	1444325	1			T1	7897		T2	8		T3	12
valid_sources[0x3b]	1503225	1			T1	7881		T2	3		T3	6
valid_sources[0x3c]	1469042	1			T1	7826		T2	11		T3	7
valid_sources[0x3d]	1363684	1			T1	8103		T2	19		T3	5
valid_sources[0x3e]	1379766	1			T1	7792		T2	3		T3	11
valid_sources[0x3f]	1356811	1			T1	7970		T2	15		T3	7
valid_sources[0x40]	2136475	1			T1	8006		T2	9		T3	6
valid_sources[0x41]	1395887	1			T1	8069		T2	3		T3	5
valid_sources[0x42]	2185229	1			T1	7898		T2	10		T3	9
valid_sources[0x43]	1363557	1			T1	8066		T2	9		T3	11
valid_sources[0x44]	1356416	1			T1	8066		T2	3		T3	16
valid_sources[0x45]	2297106	1			T1	7864		T2	13		T3	9
valid_sources[0x46]	1349302	1			T1	7916		T2	12		T3	12
valid_sources[0x47]	1375153	1			T1	7941		T2	7		T3	12
valid_sources[0x48]	1366733	1			T1	7879		T2	7		T3	12
valid_sources[0x49]	1521975	1			T1	7917		T2	15		T3	13
valid_sources[0x4a]	1373984	1			T1	7997		T2	11		T3	5
valid_sources[0x4b]	1354730	1			T1	7971		T2	6		T3	10
valid_sources[0x4c]	1479337	1			T1	7992		T2	4		T3	6
valid_sources[0x4d]	1363265	1			T1	7889		T2	4		T3	6
valid_sources[0x4e]	1376932	1			T1	8032		T2	3		T3	12
valid_sources[0x4f]	2394224	1			T1	7775		T2	8		T3	12
valid_sources[0x50]	1368155	1			T1	8010		T2	13		T3	16
valid_sources[0x51]	1363262	1			T1	7832		T2	10		T3	14
valid_sources[0x52]	1417341	1			T1	7898		T2	7		T3	4
valid_sources[0x53]	1357658	1			T1	7838		T2	11		T3	13
valid_sources[0x54]	3394576	1			T1	7821		T2	7		T3	6
valid_sources[0x55]	2275405	1			T1	7930		T2	3		T3	13
valid_sources[0x56]	2316190	1			T1	8091		T2	10		T3	11
valid_sources[0x57]	1427583	1			T1	7767		T2	5		T3	14
valid_sources[0x58]	1360329	1			T1	7805		T2	7		T3	3
valid_sources[0x59]	1371705	1			T1	8048		T2	2		T3	8
valid_sources[0x5a]	2021183	1			T1	7928		T2	8		T3	9
valid_sources[0x5b]	1360232	1			T1	7910		T2	11		T3	10
valid_sources[0x5c]	1475275	1			T1	7831		T2	7		T3	4
valid_sources[0x5d]	1367945	1			T1	7963		T2	10		T3	6
valid_sources[0x5e]	3725664	1			T1	7980		T2	6		T3	11
valid_sources[0x5f]	1354973	1			T1	7956		T2	10		T3	10
valid_sources[0x60]	1360265	1			T1	7873		T2	5		T3	5
valid_sources[0x61]	1460377	1			T1	7876		T2	11		T3	8
valid_sources[0x62]	1456323	1			T1	7986		T2	6		T3	8
valid_sources[0x63]	1362174	1			T1	7832		T2	17		T3	14
valid_sources[0x64]	1359361	1			T1	7877		T2	12		T3	4
valid_sources[0x65]	2329921	1			T1	7883		T2	5		T3	11
valid_sources[0x66]	1357743	1			T1	7965		T2	16		T3	13
valid_sources[0x67]	1364841	1			T1	7947		T2	8		T3	9
valid_sources[0x68]	1402656	1			T1	8041		T2	17		T3	5
valid_sources[0x69]	1358479	1			T1	7924		T2	17		T3	9
valid_sources[0x6a]	2213252	1			T1	8085		T2	8		T3	3
valid_sources[0x6b]	1364308	1			T1	8072		T2	9		T3	10
valid_sources[0x6c]	3878765	1			T1	7994		T2	5		T3	5
valid_sources[0x6d]	3396186	1			T1	7927		T2	9		T3	11
valid_sources[0x6e]	1357447	1			T1	7997		T2	5		T3	8
valid_sources[0x6f]	3810199	1			T1	8037		T2	14		T3	10
valid_sources[0x70]	1469839	1			T1	8013		T2	6		T3	18
valid_sources[0x71]	3764879	1			T1	7861		T2	5		T3	9
valid_sources[0x72]	1361535	1			T1	7922		T2	12		T3	10
valid_sources[0x73]	1478545	1			T1	7957		T2	14		T3	13
valid_sources[0x74]	1359799	1			T1	7890		T2	11		T3	8
valid_sources[0x75]	1361183	1			T1	7747		T2	15		T3	7
valid_sources[0x76]	1354876	1			T1	8042		T2	1		T3	11
valid_sources[0x77]	1367909	1			T1	8128		T2	2		T3	8
valid_sources[0x78]	1362837	1			T1	7875		T2	17		T3	10
valid_sources[0x79]	1358317	1			T1	7894		T2	7		T3	5
valid_sources[0x7a]	1362222	1			T1	7993		T2	6		T3	10
valid_sources[0x7b]	1370414	1			T1	7985		T2	7		T3	7
valid_sources[0x7c]	1356898	1			T1	7954		T2	7		T3	6
valid_sources[0x7d]	1379161	1			T1	7861		T2	10		T3	4
valid_sources[0x7e]	1401388	1			T1	7924		T2	6		T3	6
valid_sources[0x7f]	1360487	1			T1	7936		T2	10		T3	5
valid_sources[0x80]	2292484	1			T1	7868		T2	2		T3	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

87170666

1

T1

418003

T2

697

T3

713

values[0x0]

all_enables

biggest_size

60342619

1

T1

254665

T2

356

T3

369

values[0x1]

all_enables

biggest_size

51810509

1

T1

214768

T2

342

T3

313