Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

254744636

1

T1

114693

T2

769

T3

844

full_word

199435839

1

T1

887436

T2

1395

T3

1395

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	454180195	1			T1	203437		T2	2164		T3	2239
auto[TlIntgErrCmd]	91	1			T114	6		T115	5		T116	2
auto[TlIntgErrData]	91	1			T114	10		T115	3		T116	2
auto[TlIntgErrBoth]	98	1			T114	4		T115	2		T116	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

239283183

1

T1

110290

T2

1127

T3

1163

auto[1]

214897292

1

T1

931469

T2

1037

T3

1076

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	152084525	1			T1	684903		T2	430		T3	450
auto[TlIntgErrNone]	partial	auto[1]	102659857	1			T1	462036		T2	339		T3	394
auto[TlIntgErrNone]	full_word	auto[0]	87198539	1			T1	418003		T2	697		T3	713
auto[TlIntgErrNone]	full_word	auto[1]	112237274	1			T1	469433		T2	698		T3	682
auto[TlIntgErrCmd]	partial	auto[0]	33	1			T114	2		T115	4		T182	2
auto[TlIntgErrCmd]	partial	auto[1]	50	1			T114	3		T116	2		T182	4
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T115	1		T188	1		T189	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T114	1		T183	1		T190	1
auto[TlIntgErrData]	partial	auto[0]	43	1			T114	5		T182	3		T191	1
auto[TlIntgErrData]	partial	auto[1]	43	1			T114	3		T115	3		T116	2
auto[TlIntgErrData]	full_word	auto[0]	2	1			T114	1		T187	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	3	1			T114	1		T190	1		T192	1
auto[TlIntgErrBoth]	partial	auto[0]	34	1			T115	1		T116	1		T182	4
auto[TlIntgErrBoth]	partial	auto[1]	51	1			T114	2		T115	1		T116	5
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T193	1		T185	2		T194	1
auto[TlIntgErrBoth]	full_word	auto[1]	9	1			T114	2		T183	2		T186	2