Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	415305	0	0
entropy_period_rd_A	2147483647	828	0	0
intr_enable_rd_A	2147483647	1324	0	0
prefix_0_rd_A	2147483647	740	0	0
prefix_10_rd_A	2147483647	797	0	0
prefix_1_rd_A	2147483647	747	0	0
prefix_2_rd_A	2147483647	687	0	0
prefix_3_rd_A	2147483647	741	0	0
prefix_4_rd_A	2147483647	756	0	0
prefix_5_rd_A	2147483647	729	0	0
prefix_6_rd_A	2147483647	712	0	0
prefix_7_rd_A	2147483647	777	0	0
prefix_8_rd_A	2147483647	736	0	0
prefix_9_rd_A	2147483647	635	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	415305	0	0
T52	461925	63275	0	0
T53	0	39176	0	0
T54	0	44998	0	0
T91	0	79830	0	0
T120	0	21031	0	0
T121	0	44979	0	0
T122	0	14414	0	0
T123	0	78995	0	0
T124	0	25277	0	0
T125	0	189	0	0
T126	647241	0	0	0
T127	955603	0	0	0
T128	85344	0	0	0
T129	326123	0	0	0
T130	1434	0	0	0
T131	252639	0	0	0
T132	311852	0	0	0
T133	256693	0	0	0
T134	1670	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	828	0	0
T106	13499	42	0	0
T117	1987	3	0	0
T149	26351	212	0	0
T150	7679	27	0	0
T151	6905	15	0	0
T152	6701	6	0	0
T153	5524	8	0	0
T154	2223	2	0	0
T155	2913	15	0	0
T156	8307	18	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1324	0	0
T117	1987	2	0	0
T149	26351	228	0	0
T150	7679	27	0	0
T151	6905	43	0	0
T152	6701	41	0	0
T157	1399	20	0	0
T158	1306	22	0	0
T159	1111	17	0	0
T160	1020	18	0	0
T161	1400	13	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	740	0	0
T106	13499	43	0	0
T149	26351	212	0	0
T150	7679	16	0	0
T151	6905	16	0	0
T152	6701	16	0	0
T153	5524	15	0	0
T154	2223	2	0	0
T155	2913	6	0	0
T156	8307	16	0	0
T162	3939	4	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	797	0	0
T106	13499	46	0	0
T117	1987	1	0	0
T149	26351	207	0	0
T150	7679	13	0	0
T151	6905	12	0	0
T152	6701	7	0	0
T153	5524	18	0	0
T154	2223	7	0	0
T155	2913	13	0	0
T162	3939	3	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	747	0	0
T106	13499	38	0	0
T117	1987	5	0	0
T149	26351	186	0	0
T150	7679	22	0	0
T151	6905	21	0	0
T152	6701	30	0	0
T153	5524	7	0	0
T154	2223	2	0	0
T155	2913	8	0	0
T162	3939	14	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	687	0	0
T106	13499	40	0	0
T117	1987	8	0	0
T149	26351	191	0	0
T150	7679	14	0	0
T151	6905	30	0	0
T152	6701	22	0	0
T153	5524	15	0	0
T154	2223	6	0	0
T155	2913	10	0	0
T163	6175	1	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	741	0	0
T106	13499	17	0	0
T117	1987	7	0	0
T149	26351	224	0	0
T150	7679	13	0	0
T151	6905	35	0	0
T152	6701	10	0	0
T153	5524	12	0	0
T154	2223	9	0	0
T155	2913	12	0	0
T162	3939	10	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	756	0	0
T106	13499	21	0	0
T117	1987	3	0	0
T149	26351	254	0	0
T150	7679	16	0	0
T151	6905	16	0	0
T152	6701	40	0	0
T153	5524	20	0	0
T155	2913	11	0	0
T162	3939	6	0	0
T163	6175	3	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	729	0	0
T106	13499	40	0	0
T117	1987	2	0	0
T149	26351	190	0	0
T150	7679	15	0	0
T151	6905	11	0	0
T152	6701	55	0	0
T153	5524	16	0	0
T154	2223	5	0	0
T155	2913	8	0	0
T162	3939	4	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	712	0	0
T106	13499	12	0	0
T149	26351	226	0	0
T150	7679	12	0	0
T151	6905	40	0	0
T152	6701	33	0	0
T153	5524	14	0	0
T154	2223	1	0	0
T155	2913	10	0	0
T156	8307	20	0	0
T162	3939	6	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	777	0	0
T106	13499	35	0	0
T149	26351	246	0	0
T150	7679	11	0	0
T151	6905	15	0	0
T152	6701	43	0	0
T153	5524	16	0	0
T154	2223	3	0	0
T155	2913	11	0	0
T156	8307	23	0	0
T164	12834	1	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	736	0	0
T106	13499	32	0	0
T117	1987	2	0	0
T149	26351	234	0	0
T150	7679	13	0	0
T151	6905	1	0	0
T152	6701	37	0	0
T153	5524	12	0	0
T154	2223	7	0	0
T155	2913	9	0	0
T156	8307	11	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	635	0	0
T106	13499	23	0	0
T117	1987	1	0	0
T149	26351	194	0	0
T150	7679	18	0	0
T151	6905	32	0	0
T152	6701	9	0	0
T153	5524	22	0	0
T154	2223	1	0	0
T155	2913	16	0	0
T162	3939	1	0	0