Group : kmac_env_pkg::app_cg_wrap::app_cfg_reg_cg
Group Instance : AppKeymgr_cg_(1)
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance AppKeymgr_cg_(1)
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
3 |
0 |
3 |
100.00 |
Variables for Group Instance AppKeymgr_cg_(1)
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
sw_configured_hash_mode |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : AppLc_cg_(1)
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance AppLc_cg_(1)
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
3 |
0 |
3 |
100.00 |
Variables for Group Instance AppLc_cg_(1)
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
sw_configured_hash_mode |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : AppRom_cg_(1)
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance AppRom_cg_(1)
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
3 |
0 |
3 |
100.00 |
Variables for Group Instance AppRom_cg_(1)
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
sw_configured_hash_mode |
3 |
0 |
3 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable sw_configured_hash_mode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for sw_configured_hash_mode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
cshake |
947 |
1 |
|
|
T16 |
9 |
|
T22 |
1 |
|
T23 |
11 |
shake |
1009 |
1 |
|
|
T16 |
16 |
|
T22 |
3 |
|
T23 |
5 |
sha3 |
988 |
1 |
|
|
T16 |
15 |
|
T22 |
2 |
|
T23 |
2 |
Summary for Variable sw_configured_hash_mode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for sw_configured_hash_mode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
cshake |
439 |
1 |
|
|
T16 |
4 |
|
T28 |
1 |
|
T24 |
4 |
shake |
446 |
1 |
|
|
T16 |
4 |
|
T28 |
4 |
|
T24 |
1 |
sha3 |
490 |
1 |
|
|
T16 |
5 |
|
T22 |
1 |
|
T23 |
1 |
Summary for Variable sw_configured_hash_mode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for sw_configured_hash_mode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
cshake |
476 |
1 |
|
|
T16 |
7 |
|
T22 |
2 |
|
T23 |
1 |
shake |
487 |
1 |
|
|
T16 |
3 |
|
T24 |
4 |
|
T41 |
1 |
sha3 |
518 |
1 |
|
|
T16 |
5 |
|
T23 |
1 |
|
T28 |
1 |
0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |