Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

256462788

1

T1

16

T2

284259

T3

917

full_word

199987153

1

T1

181

T2

183368

T3

5044

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	456449641	1			T1	197		T2	467627		T3	5961
auto[TlIntgErrCmd]	93	1			T105	3		T106	3		T107	5
auto[TlIntgErrData]	95	1			T105	1		T106	9		T107	9
auto[TlIntgErrBoth]	112	1			T105	6		T106	8		T107	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

240043758

1

T1

93

T2

240869

T3

4028

auto[1]

216406183

1

T1

104

T2

226758

T3

1933

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	153118901	1			T1	7		T2	168498		T3	507
auto[TlIntgErrNone]	partial	auto[1]	103343614	1			T1	9		T2	115761		T3	410
auto[TlIntgErrNone]	full_word	auto[0]	86924715	1			T1	86		T2	72371		T3	3521
auto[TlIntgErrNone]	full_word	auto[1]	113062411	1			T1	95		T2	110997		T3	1523
auto[TlIntgErrCmd]	partial	auto[0]	34	1			T105	1		T107	3		T155	5
auto[TlIntgErrCmd]	partial	auto[1]	52	1			T105	1		T106	3		T107	2
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T158	1		T159	1		T160	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T105	1		T157	1		T161	1
auto[TlIntgErrData]	partial	auto[0]	46	1			T105	1		T106	6		T107	4
auto[TlIntgErrData]	partial	auto[1]	39	1			T106	3		T107	5		T155	2
auto[TlIntgErrData]	full_word	auto[0]	5	1			T158	2		T161	1		T160	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T157	1		T161	1		T162	1
auto[TlIntgErrBoth]	partial	auto[0]	51	1			T105	5		T106	5		T107	1
auto[TlIntgErrBoth]	partial	auto[1]	51	1			T106	2		T107	4		T155	4
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T105	1		T157	1		T163	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T106	1		T107	1		T157	2