Module Definition
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Module : sha3
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.32 97.56 88.89 81.82 93.33 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/sha3.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_sha3 95.96 97.56 88.89 100.00 93.33 100.00



Module Instance : tb.dut.u_sha3

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.96 97.56 88.89 100.00 93.33 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.16 91.91 88.51 100.00 80.56 92.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.24 96.27 93.33 100.00 100.00 93.85 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_keccak 81.47 81.77 88.24 100.00 40.00 78.79 100.00
u_pad 96.28 99.42 88.37 100.00 94.12 95.79 100.00
u_state_regs 100.00 100.00 100.00 100.00

Line Coverage for Module : sha3
Line No.TotalCoveredPercent
TOTAL828097.56
CONT_ASSIGN13811100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN17211100.00
CONT_ASSIGN17311100.00
CONT_ASSIGN17811100.00
CONT_ASSIGN17911100.00
ALWAYS18455100.00
ALWAYS19833100.00
CONT_ASSIGN20311100.00
ALWAYS20766100.00
CONT_ASSIGN21411100.00
CONT_ASSIGN21711100.00
CONT_ASSIGN21811100.00
CONT_ASSIGN22011100.00
ALWAYS22733100.00
ALWAYS2373838100.00
ALWAYS33233100.00
ALWAYS349121083.33
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/sha3.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/sha3.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
138 1 1
144 1 1
148 1 1
172 1 1
173 1 1
178 1 1
179 1 1
184 1 1
185 1 1
186 1 1
188 1 1
189 1 1
198 2 2
199 1 1
203 1 1
207 2 2
208 2 2
209 1 1
210 1 1
MISSING_ELSE
214 1 1
217 1 1
218 1 1
220 1 1
227 3 3
237 1 1
240 1 1
241 1 1
242 1 1
243 1 1
245 1 1
247 1 1
248 1 1
250 1 1
252 1 1
254 1 1
255 1 1
257 1 1
259 1 1
264 1 1
265 1 1
267 1 1
268 1 1
269 1 1
271 1 1
276 1 1
277 1 1
279 1 1
281 1 1
282 1 1
284 1 1
285 1 1
286 1 1
288 1 1
290 1 1
295 1 1
296 1 1
298 1 1
303 1 1
308 1 1
309 1 1
321 1 1
322 1 1
MISSING_ELSE
332 1 1
333 1 1
334 1 1
349 1 1
351 1 1
353 1 1
355 1 1
MISSING_ELSE
364 1 1
366 1 1
MISSING_ELSE
375 1 1
376 0 1
MISSING_ELSE
385 1 1
387 1 1
MISSING_ELSE
396 1 1
398 0 1
MISSING_ELSE


Cond Coverage for Module : sha3
TotalCoveredPercent
Conditions272488.89
Logical272488.89
Non-Logical00
Event00

 LINE       138
 EXPRESSION (round_count_error | msg_count_error)
             --------1--------   -------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT10,T11,T12
10CoveredT10,T11,T12

 LINE       144
 EXPRESSION (sha3_state_error | keccak_round_state_error | sha3pad_state_error)
             --------1-------   ------------2-----------   ---------3---------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT10,T11,T12
010CoveredT10,T11,T12
100CoveredT10,T11,T12

 LINE       173
 EXPRESSION ((sha3pad_keccak_run || sw_keccak_run) ? 1'b1 : (keccak_complete ? 1'b0 : keccak_run_req_q))
             ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       173
 SUB-EXPRESSION (sha3pad_keccak_run || sw_keccak_run)
                 ---------1--------    ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT13,T16,T19
10CoveredT2,T3,T4

 LINE       173
 SUB-EXPRESSION (keccak_complete ? 1'b0 : keccak_run_req_q)
                 -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       178
 EXPRESSION (run_req_o & run_ack_i & ((~keccak_triggered_q)))
             ----1----   ----2----   -----------3-----------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Unreachable
110CoveredT2,T3,T4
111CoveredT2,T3,T4

 LINE       179
 EXPRESSION (keccak_run ? 1'b1 : (keccak_complete ? 1'b0 : keccak_triggered_q))
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       179
 SUB-EXPRESSION (keccak_complete ? 1'b0 : keccak_triggered_q)
                 -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       264
 EXPRESSION (process_i && ((!processing)))
             ----1----    -------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT2,T3,T4

 LINE       375
 EXPRESSION (start_i || process_i)
             ---1---    ----2----
-1--2-StatusTests
00CoveredT2,T3,T4
01Not Covered
10Not Covered

FSM Coverage for Module : sha3
Summary for FSM :: st
TotalCoveredPercent
States 6 6 100.00 (Not included in score)
Transitions 11 9 81.82
Sequences 0 0

State, Transition and Sequence Details for FSM :: st
statesLine No.CoveredTests
StAbsorb_sparse 255 Covered T1,T2,T3
StFlush_sparse 286 Covered T2,T3,T4
StIdle_sparse 259 Covered T1,T2,T3
StManualRun_sparse 282 Covered T13,T16,T19
StSqueeze_sparse 269 Covered T2,T3,T4
StTerminalError_sparse 308 Covered T1,T5,T6


transitionsLine No.CoveredTests
StAbsorb_sparse->StSqueeze_sparse 269 Covered T2,T3,T4
StAbsorb_sparse->StTerminalError_sparse 322 Covered T1,T5,T6
StFlush_sparse->StIdle_sparse 303 Covered T2,T3,T4
StFlush_sparse->StTerminalError_sparse 322 Not Covered
StIdle_sparse->StAbsorb_sparse 255 Covered T1,T2,T3
StIdle_sparse->StTerminalError_sparse 322 Covered T10,T11,T37
StManualRun_sparse->StSqueeze_sparse 296 Covered T13,T16,T19
StManualRun_sparse->StTerminalError_sparse 322 Not Covered
StSqueeze_sparse->StFlush_sparse 286 Covered T2,T3,T4
StSqueeze_sparse->StManualRun_sparse 282 Covered T13,T16,T19
StSqueeze_sparse->StTerminalError_sparse 322 Covered T57,T58,T59



Branch Coverage for Module : sha3
Line No.TotalCoveredPercent
Branches 45 42 93.33
TERNARY 173 3 3 100.00
TERNARY 179 3 3 100.00
IF 184 2 2 100.00
IF 198 2 2 100.00
IF 207 4 4 100.00
IF 227 2 2 100.00
CASE 252 13 13 100.00
IF 321 2 2 100.00
CASE 332 3 2 66.67
CASE 351 11 9 81.82

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/sha3.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/sha3.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 173 ((sha3pad_keccak_run || sw_keccak_run)) ? -2-: 173 (keccak_complete) ?

Branches:
-1--2-StatusTests
1 - Covered T2,T3,T4
0 1 Covered T2,T3,T4
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 179 (keccak_run) ? -2-: 179 (keccak_complete) ?

Branches:
-1--2-StatusTests
1 - Covered T2,T3,T4
0 1 Covered T2,T3,T4
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 184 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 198 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 207 if ((!rst_ni)) -2-: 208 if (process_i) -3-: 209 if (prim_mubi_pkg::mubi4_test_true_strict(absorbed))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T2,T3,T4
0 0 1 Covered T2,T3,T4
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 227 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 252 case (st) -2-: 254 if (start_i) -3-: 264 if ((process_i && (!processing))) -4-: 268 if (prim_mubi_pkg::mubi4_test_true_strict(absorbed)) -5-: 281 if (run_i) -6-: 285 if (prim_mubi_pkg::mubi4_test_true_strict(done_i)) -7-: 295 if (keccak_complete)

Branches:
-1--2--3--4--5--6--7-StatusTests
StIdle_sparse 1 - - - - - Covered T1,T2,T3
StIdle_sparse 0 - - - - - Covered T1,T2,T3
StAbsorb_sparse - 1 - - - - Covered T2,T3,T4
StAbsorb_sparse - 0 1 - - - Covered T2,T3,T4
StAbsorb_sparse - 0 0 - - - Covered T1,T2,T3
StSqueeze_sparse - - - 1 - - Covered T13,T16,T19
StSqueeze_sparse - - - 0 1 - Covered T2,T3,T4
StSqueeze_sparse - - - 0 0 - Covered T2,T3,T4
StManualRun_sparse - - - - - 1 Covered T13,T16,T19
StManualRun_sparse - - - - - 0 Covered T13,T16,T19
StFlush_sparse - - - - - - Covered T2,T3,T4
StTerminalError_sparse - - - - - - Covered T1,T5,T6
default - - - - - - Covered T10,T11,T12


LineNo. Expression -1-: 321 if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 332 case (mux_sel)

Branches:
-1-StatusTests
MuxGuard Covered T1,T2,T3
MuxRelease Covered T2,T3,T4
default Not Covered


LineNo. Expression -1-: 351 case (st) -2-: 353 if (((process_i || run_i) || prim_mubi_pkg::mubi4_test_true_loose(done_i))) -3-: 364 if ((((start_i || run_i) || prim_mubi_pkg::mubi4_test_true_loose(done_i)) || (process_i && processing))) -4-: 375 if ((start_i || process_i)) -5-: 385 if ((((start_i || process_i) || run_i) || prim_mubi_pkg::mubi4_test_true_loose(done_i))) -6-: 396 if ((((start_i || process_i) || run_i) || prim_mubi_pkg::mubi4_test_true_loose(done_i)))

Branches:
-1--2--3--4--5--6-StatusTests
StIdle_sparse 1 - - - - Covered T22,T24,T25
StIdle_sparse 0 - - - - Covered T1,T2,T3
StAbsorb_sparse - 1 - - - Covered T22,T24,T25
StAbsorb_sparse - 0 - - - Covered T1,T2,T3
StSqueeze_sparse - - 1 - - Not Covered
StSqueeze_sparse - - 0 - - Covered T2,T3,T4
StManualRun_sparse - - - 1 - Covered T22,T24,T55
StManualRun_sparse - - - 0 - Covered T13,T16,T19
StFlush_sparse - - - - 1 Not Covered
StFlush_sparse - - - - 0 Covered T2,T3,T4
default - - - - - Covered T1,T5,T6


Assert Coverage for Module : sha3
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 7 7 100.00 7 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 7 7 100.00 7 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
ErrDetection_A 2147483647 6639186 0 0
FsmKnown_A 2147483647 2147483647 0 0
KeccakIdleWhenNoRunHs_A 2147483647 77409944 0 0
MuxSelKnown_A 2147483647 2147483647 0 0
SwRunInSqueezing_a 2147483647 147201 0 0
gen_chk_digest_unmasked.StateZeroInvalid_A 2147483647 2147483647 0 0
u_state_regs_A 2147483647 2147483647 0 0


ErrDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 6639186 0 0
T22 864424 15817 0 0
T23 92653 0 0 0
T24 623921 179968 0 0
T25 0 545 0 0
T28 756654 0 0 0
T29 135458 0 0 0
T39 145962 0 0 0
T40 21887 0 0 0
T41 339108 0 0 0
T42 0 202990 0 0
T51 1108 0 0 0
T55 0 91001 0 0
T79 0 245343 0 0
T80 0 507521 0 0
T81 0 42832 0 0
T82 0 217901 0 0
T83 0 104253 0 0
T84 167583 0 0 0

FsmKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 4726 4581 0 0
T2 960577 960480 0 0
T3 46106 46016 0 0
T4 6191 6141 0 0
T5 3259 3101 0 0
T13 304991 304981 0 0
T14 16057 15979 0 0
T15 420790 420731 0 0
T16 165511 165503 0 0
T17 494627 494620 0 0

KeccakIdleWhenNoRunHs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 77409944 0 0
T2 960577 130248 0 0
T3 46106 1776 0 0
T4 6191 744 0 0
T5 3259 24 0 0
T13 304991 186072 0 0
T14 16057 744 0 0
T15 420790 11736 0 0
T16 165511 30144 0 0
T17 494627 315528 0 0
T18 117926 1224 0 0

MuxSelKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 4726 4581 0 0
T2 960577 960480 0 0
T3 46106 46016 0 0
T4 6191 6141 0 0
T5 3259 3101 0 0
T13 304991 304981 0 0
T14 16057 15979 0 0
T15 420790 420731 0 0
T16 165511 165503 0 0
T17 494627 494620 0 0

SwRunInSqueezing_a
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 147201 0 0
T5 3259 0 0 0
T13 304991 639 0 0
T14 16057 0 0 0
T15 420790 0 0 0
T16 165511 359 0 0
T17 494627 0 0 0
T18 117926 0 0 0
T19 25181 29 0 0
T22 864424 35 0 0
T23 92653 0 0 0
T24 0 958 0 0
T28 0 163 0 0
T29 0 637 0 0
T39 0 571 0 0
T41 0 247 0 0
T84 0 251 0 0

gen_chk_digest_unmasked.StateZeroInvalid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 4726 4581 0 0
T2 960577 910514 0 0
T3 46106 27912 0 0
T4 6191 4512 0 0
T5 3259 3101 0 0
T13 304991 238518 0 0
T14 16057 11551 0 0
T15 420790 250253 0 0
T16 165511 122437 0 0
T17 494627 450460 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 4726 4581 0 0
T2 960577 960480 0 0
T3 46106 46016 0 0
T4 6191 6141 0 0
T5 3259 3101 0 0
T13 304991 304981 0 0
T14 16057 15979 0 0
T15 420790 420731 0 0
T16 165511 165503 0 0
T17 494627 494620 0 0

Line Coverage for Instance : tb.dut.u_sha3
Line No.TotalCoveredPercent
TOTAL828097.56
CONT_ASSIGN13811100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN17211100.00
CONT_ASSIGN17311100.00
CONT_ASSIGN17811100.00
CONT_ASSIGN17911100.00
ALWAYS18455100.00
ALWAYS19833100.00
CONT_ASSIGN20311100.00
ALWAYS20766100.00
CONT_ASSIGN21411100.00
CONT_ASSIGN21711100.00
CONT_ASSIGN21811100.00
CONT_ASSIGN22011100.00
ALWAYS22733100.00
ALWAYS2373838100.00
ALWAYS33233100.00
ALWAYS349121083.33
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/sha3.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/sha3.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
138 1 1
144 1 1
148 1 1
172 1 1
173 1 1
178 1 1
179 1 1
184 1 1
185 1 1
186 1 1
188 1 1
189 1 1
198 2 2
199 1 1
203 1 1
207 2 2
208 2 2
209 1 1
210 1 1
MISSING_ELSE
214 1 1
217 1 1
218 1 1
220 1 1
227 3 3
237 1 1
240 1 1
241 1 1
242 1 1
243 1 1
245 1 1
247 1 1
248 1 1
250 1 1
252 1 1
254 1 1
255 1 1
257 1 1
259 1 1
264 1 1
265 1 1
267 1 1
268 1 1
269 1 1
271 1 1
276 1 1
277 1 1
279 1 1
281 1 1
282 1 1
284 1 1
285 1 1
286 1 1
288 1 1
290 1 1
295 1 1
296 1 1
298 1 1
303 1 1
308 1 1
309 1 1
321 1 1
322 1 1
MISSING_ELSE
332 1 1
333 1 1
334 1 1
349 1 1
351 1 1
353 1 1
355 1 1
MISSING_ELSE
364 1 1
366 1 1
MISSING_ELSE
375 1 1
376 0 1
MISSING_ELSE
385 1 1
387 1 1
MISSING_ELSE
396 1 1
398 0 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_sha3
TotalCoveredPercent
Conditions272488.89
Logical272488.89
Non-Logical00
Event00

 LINE       138
 EXPRESSION (round_count_error | msg_count_error)
             --------1--------   -------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT10,T11,T12
10CoveredT10,T11,T12

 LINE       144
 EXPRESSION (sha3_state_error | keccak_round_state_error | sha3pad_state_error)
             --------1-------   ------------2-----------   ---------3---------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT10,T11,T12
010CoveredT10,T11,T12
100CoveredT10,T11,T12

 LINE       173
 EXPRESSION ((sha3pad_keccak_run || sw_keccak_run) ? 1'b1 : (keccak_complete ? 1'b0 : keccak_run_req_q))
             ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       173
 SUB-EXPRESSION (sha3pad_keccak_run || sw_keccak_run)
                 ---------1--------    ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT13,T16,T19
10CoveredT2,T3,T4

 LINE       173
 SUB-EXPRESSION (keccak_complete ? 1'b0 : keccak_run_req_q)
                 -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       178
 EXPRESSION (run_req_o & run_ack_i & ((~keccak_triggered_q)))
             ----1----   ----2----   -----------3-----------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Unreachable
110CoveredT2,T3,T4
111CoveredT2,T3,T4

 LINE       179
 EXPRESSION (keccak_run ? 1'b1 : (keccak_complete ? 1'b0 : keccak_triggered_q))
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       179
 SUB-EXPRESSION (keccak_complete ? 1'b0 : keccak_triggered_q)
                 -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       264
 EXPRESSION (process_i && ((!processing)))
             ----1----    -------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT2,T3,T4

 LINE       375
 EXPRESSION (start_i || process_i)
             ---1---    ----2----
-1--2-StatusTests
00CoveredT2,T3,T4
01Not Covered
10Not Covered

FSM Coverage for Instance : tb.dut.u_sha3
Summary for FSM :: st
TotalCoveredPercent
States 6 6 100.00 (Not included in score)
Transitions 9 9 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: st
statesLine No.CoveredTests
StAbsorb_sparse 255 Covered T1,T2,T3
StFlush_sparse 286 Covered T2,T3,T4
StIdle_sparse 259 Covered T1,T2,T3
StManualRun_sparse 282 Covered T13,T16,T19
StSqueeze_sparse 269 Covered T2,T3,T4
StTerminalError_sparse 308 Covered T1,T5,T6


transitionsLine No.CoveredTestsExclude Annotation
StAbsorb_sparse->StSqueeze_sparse 269 Covered T2,T3,T4
StAbsorb_sparse->StTerminalError_sparse 322 Covered T1,T5,T6
StFlush_sparse->StIdle_sparse 303 Covered T2,T3,T4
StFlush_sparse->StTerminalError_sparse 322 Excluded [LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
StIdle_sparse->StAbsorb_sparse 255 Covered T1,T2,T3
StIdle_sparse->StTerminalError_sparse 322 Covered T10,T11,T37
StManualRun_sparse->StSqueeze_sparse 296 Covered T13,T16,T19
StManualRun_sparse->StTerminalError_sparse 322 Excluded [LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
StSqueeze_sparse->StFlush_sparse 286 Covered T2,T3,T4
StSqueeze_sparse->StManualRun_sparse 282 Covered T13,T16,T19
StSqueeze_sparse->StTerminalError_sparse 322 Covered T57,T58,T59



Branch Coverage for Instance : tb.dut.u_sha3
Line No.TotalCoveredPercent
Branches 45 42 93.33
TERNARY 173 3 3 100.00
TERNARY 179 3 3 100.00
IF 184 2 2 100.00
IF 198 2 2 100.00
IF 207 4 4 100.00
IF 227 2 2 100.00
CASE 252 13 13 100.00
IF 321 2 2 100.00
CASE 332 3 2 66.67
CASE 351 11 9 81.82

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/sha3.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/sha3.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 173 ((sha3pad_keccak_run || sw_keccak_run)) ? -2-: 173 (keccak_complete) ?

Branches:
-1--2-StatusTests
1 - Covered T2,T3,T4
0 1 Covered T2,T3,T4
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 179 (keccak_run) ? -2-: 179 (keccak_complete) ?

Branches:
-1--2-StatusTests
1 - Covered T2,T3,T4
0 1 Covered T2,T3,T4
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 184 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 198 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 207 if ((!rst_ni)) -2-: 208 if (process_i) -3-: 209 if (prim_mubi_pkg::mubi4_test_true_strict(absorbed))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T2,T3,T4
0 0 1 Covered T2,T3,T4
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 227 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 252 case (st) -2-: 254 if (start_i) -3-: 264 if ((process_i && (!processing))) -4-: 268 if (prim_mubi_pkg::mubi4_test_true_strict(absorbed)) -5-: 281 if (run_i) -6-: 285 if (prim_mubi_pkg::mubi4_test_true_strict(done_i)) -7-: 295 if (keccak_complete)

Branches:
-1--2--3--4--5--6--7-StatusTests
StIdle_sparse 1 - - - - - Covered T1,T2,T3
StIdle_sparse 0 - - - - - Covered T1,T2,T3
StAbsorb_sparse - 1 - - - - Covered T2,T3,T4
StAbsorb_sparse - 0 1 - - - Covered T2,T3,T4
StAbsorb_sparse - 0 0 - - - Covered T1,T2,T3
StSqueeze_sparse - - - 1 - - Covered T13,T16,T19
StSqueeze_sparse - - - 0 1 - Covered T2,T3,T4
StSqueeze_sparse - - - 0 0 - Covered T2,T3,T4
StManualRun_sparse - - - - - 1 Covered T13,T16,T19
StManualRun_sparse - - - - - 0 Covered T13,T16,T19
StFlush_sparse - - - - - - Covered T2,T3,T4
StTerminalError_sparse - - - - - - Covered T1,T5,T6
default - - - - - - Covered T10,T11,T12


LineNo. Expression -1-: 321 if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 332 case (mux_sel)

Branches:
-1-StatusTests
MuxGuard Covered T1,T2,T3
MuxRelease Covered T2,T3,T4
default Not Covered


LineNo. Expression -1-: 351 case (st) -2-: 353 if (((process_i || run_i) || prim_mubi_pkg::mubi4_test_true_loose(done_i))) -3-: 364 if ((((start_i || run_i) || prim_mubi_pkg::mubi4_test_true_loose(done_i)) || (process_i && processing))) -4-: 375 if ((start_i || process_i)) -5-: 385 if ((((start_i || process_i) || run_i) || prim_mubi_pkg::mubi4_test_true_loose(done_i))) -6-: 396 if ((((start_i || process_i) || run_i) || prim_mubi_pkg::mubi4_test_true_loose(done_i)))

Branches:
-1--2--3--4--5--6-StatusTests
StIdle_sparse 1 - - - - Covered T22,T24,T25
StIdle_sparse 0 - - - - Covered T1,T2,T3
StAbsorb_sparse - 1 - - - Covered T22,T24,T25
StAbsorb_sparse - 0 - - - Covered T1,T2,T3
StSqueeze_sparse - - 1 - - Not Covered
StSqueeze_sparse - - 0 - - Covered T2,T3,T4
StManualRun_sparse - - - 1 - Covered T22,T24,T55
StManualRun_sparse - - - 0 - Covered T13,T16,T19
StFlush_sparse - - - - 1 Not Covered
StFlush_sparse - - - - 0 Covered T2,T3,T4
default - - - - - Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_sha3
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 7 7 100.00 7 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 7 7 100.00 7 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
ErrDetection_A 2147483647 6639186 0 0
FsmKnown_A 2147483647 2147483647 0 0
KeccakIdleWhenNoRunHs_A 2147483647 77409944 0 0
MuxSelKnown_A 2147483647 2147483647 0 0
SwRunInSqueezing_a 2147483647 147201 0 0
gen_chk_digest_unmasked.StateZeroInvalid_A 2147483647 2147483647 0 0
u_state_regs_A 2147483647 2147483647 0 0


ErrDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 6639186 0 0
T22 864424 15817 0 0
T23 92653 0 0 0
T24 623921 179968 0 0
T25 0 545 0 0
T28 756654 0 0 0
T29 135458 0 0 0
T39 145962 0 0 0
T40 21887 0 0 0
T41 339108 0 0 0
T42 0 202990 0 0
T51 1108 0 0 0
T55 0 91001 0 0
T79 0 245343 0 0
T80 0 507521 0 0
T81 0 42832 0 0
T82 0 217901 0 0
T83 0 104253 0 0
T84 167583 0 0 0

FsmKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 4726 4581 0 0
T2 960577 960480 0 0
T3 46106 46016 0 0
T4 6191 6141 0 0
T5 3259 3101 0 0
T13 304991 304981 0 0
T14 16057 15979 0 0
T15 420790 420731 0 0
T16 165511 165503 0 0
T17 494627 494620 0 0

KeccakIdleWhenNoRunHs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 77409944 0 0
T2 960577 130248 0 0
T3 46106 1776 0 0
T4 6191 744 0 0
T5 3259 24 0 0
T13 304991 186072 0 0
T14 16057 744 0 0
T15 420790 11736 0 0
T16 165511 30144 0 0
T17 494627 315528 0 0
T18 117926 1224 0 0

MuxSelKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 4726 4581 0 0
T2 960577 960480 0 0
T3 46106 46016 0 0
T4 6191 6141 0 0
T5 3259 3101 0 0
T13 304991 304981 0 0
T14 16057 15979 0 0
T15 420790 420731 0 0
T16 165511 165503 0 0
T17 494627 494620 0 0

SwRunInSqueezing_a
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 147201 0 0
T5 3259 0 0 0
T13 304991 639 0 0
T14 16057 0 0 0
T15 420790 0 0 0
T16 165511 359 0 0
T17 494627 0 0 0
T18 117926 0 0 0
T19 25181 29 0 0
T22 864424 35 0 0
T23 92653 0 0 0
T24 0 958 0 0
T28 0 163 0 0
T29 0 637 0 0
T39 0 571 0 0
T41 0 247 0 0
T84 0 251 0 0

gen_chk_digest_unmasked.StateZeroInvalid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 4726 4581 0 0
T2 960577 910514 0 0
T3 46106 27912 0 0
T4 6191 4512 0 0
T5 3259 3101 0 0
T13 304991 238518 0 0
T14 16057 11551 0 0
T15 420790 250253 0 0
T16 165511 122437 0 0
T17 494627 450460 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 4726 4581 0 0
T2 960577 960480 0 0
T3 46106 46016 0 0
T4 6191 6141 0 0
T5 3259 3101 0 0
T13 304991 304981 0 0
T14 16057 15979 0 0
T15 420790 420731 0 0
T16 165511 165503 0 0
T17 494627 494620 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%