Module Definition
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Module : sha3pad_assert_if
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_cov_0/sha3pad_assert_if.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.sha3pad_assert_cov_if 100.00 100.00



Module Instance : tb.dut.sha3pad_assert_cov_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.24 96.27 93.33 100.00 100.00 93.85 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : sha3pad_assert_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
ProcessToRun_A 2147483647 347012 0 0
RunThenComplete_M 2147483647 3078208 0 0


ProcessToRun_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 347012 0 0
T2 960577 246 0 0
T3 46106 30 0 0
T4 6191 9 0 0
T5 3259 0 0 0
T13 304991 190 0 0
T14 16057 9 0 0
T15 420790 197 0 0
T16 165511 173 0 0
T17 494627 2337 0 0
T18 117926 17 0 0
T19 0 10 0 0

RunThenComplete_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 3078208 0 0
T2 960577 5427 0 0
T3 46106 74 0 0
T4 6191 31 0 0
T5 3259 1 0 0
T13 304991 7114 0 0
T14 16057 31 0 0
T15 420790 489 0 0
T16 165511 897 0 0
T17 494627 13147 0 0
T18 117926 51 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%