Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	448003	0	0
entropy_period_rd_A	2147483647	2055	0	0
intr_enable_rd_A	2147483647	2495	0	0
prefix_0_rd_A	2147483647	1954	0	0
prefix_10_rd_A	2147483647	2104	0	0
prefix_1_rd_A	2147483647	2026	0	0
prefix_2_rd_A	2147483647	2034	0	0
prefix_3_rd_A	2147483647	1905	0	0
prefix_4_rd_A	2147483647	1884	0	0
prefix_5_rd_A	2147483647	1984	0	0
prefix_6_rd_A	2147483647	2069	0	0
prefix_7_rd_A	2147483647	2068	0	0
prefix_8_rd_A	2147483647	2003	0	0
prefix_9_rd_A	2147483647	2002	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	448003	0	0
T22	864424	81709	0	0
T23	92653	0	0	0
T24	623921	0	0	0
T25	0	41481	0	0
T28	756654	0	0	0
T29	135458	0	0	0
T39	145962	0	0	0
T40	21887	0	0	0
T41	339108	0	0	0
T51	1108	0	0	0
T54	0	22333	0	0
T84	167583	0	0	0
T86	0	64036	0	0
T111	0	70877	0	0
T112	0	42342	0	0
T113	0	30193	0	0
T114	0	91915	0	0
T115	0	157	0	0
T116	0	1	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2055	0	0
T22	864424	172	0	0
T23	92653	0	0	0
T24	623921	0	0	0
T25	0	65	0	0
T28	756654	0	0	0
T29	135458	0	0	0
T39	145962	0	0	0
T40	21887	0	0	0
T41	339108	0	0	0
T51	1108	0	0	0
T84	167583	0	0	0
T90	0	15	0	0
T91	0	10	0	0
T107	0	145	0	0
T132	0	7	0	0
T133	0	1	0	0
T134	0	1	0	0
T135	0	248	0	0
T136	0	9	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2495	0	0
T22	864424	102	0	0
T23	92653	0	0	0
T24	623921	0	0	0
T25	0	22	0	0
T28	756654	0	0	0
T29	135458	0	0	0
T39	145962	0	0	0
T40	21887	0	0	0
T41	339108	0	0	0
T51	1108	0	0	0
T84	167583	0	0	0
T90	0	14	0	0
T91	0	5	0	0
T108	0	12	0	0
T109	0	2	0	0
T110	0	7	0	0
T132	0	7	0	0
T133	0	9	0	0
T137	0	39	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1954	0	0
T22	864424	163	0	0
T23	92653	0	0	0
T24	623921	0	0	0
T25	0	25	0	0
T28	756654	0	0	0
T29	135458	0	0	0
T39	145962	0	0	0
T40	21887	0	0	0
T41	339108	0	0	0
T51	1108	0	0	0
T84	167583	0	0	0
T90	0	18	0	0
T91	0	9	0	0
T107	0	77	0	0
T132	0	9	0	0
T133	0	3	0	0
T135	0	390	0	0
T137	0	42	0	0
T138	0	7	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2104	0	0
T22	864424	196	0	0
T23	92653	0	0	0
T24	623921	0	0	0
T25	0	101	0	0
T28	756654	0	0	0
T29	135458	0	0	0
T39	145962	0	0	0
T40	21887	0	0	0
T41	339108	0	0	0
T51	1108	0	0	0
T84	167583	0	0	0
T90	0	13	0	0
T91	0	1	0	0
T107	0	67	0	0
T132	0	2	0	0
T133	0	8	0	0
T135	0	430	0	0
T136	0	2	0	0
T137	0	1	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2026	0	0
T22	864424	172	0	0
T23	92653	0	0	0
T24	623921	0	0	0
T25	0	94	0	0
T28	756654	0	0	0
T29	135458	0	0	0
T39	145962	0	0	0
T40	21887	0	0	0
T41	339108	0	0	0
T51	1108	0	0	0
T84	167583	0	0	0
T90	0	17	0	0
T91	0	13	0	0
T107	0	74	0	0
T132	0	10	0	0
T133	0	1	0	0
T135	0	460	0	0
T136	0	7	0	0
T137	0	40	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2034	0	0
T22	864424	228	0	0
T23	92653	0	0	0
T24	623921	0	0	0
T25	0	42	0	0
T28	756654	0	0	0
T29	135458	0	0	0
T39	145962	0	0	0
T40	21887	0	0	0
T41	339108	0	0	0
T51	1108	0	0	0
T84	167583	0	0	0
T90	0	11	0	0
T91	0	8	0	0
T107	0	100	0	0
T132	0	5	0	0
T135	0	407	0	0
T136	0	15	0	0
T137	0	16	0	0
T139	0	1	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1905	0	0
T22	864424	158	0	0
T23	92653	0	0	0
T24	623921	0	0	0
T25	0	53	0	0
T28	756654	0	0	0
T29	135458	0	0	0
T39	145962	0	0	0
T40	21887	0	0	0
T41	339108	0	0	0
T51	1108	0	0	0
T84	167583	0	0	0
T90	0	18	0	0
T91	0	5	0	0
T107	0	88	0	0
T132	0	6	0	0
T135	0	430	0	0
T136	0	32	0	0
T137	0	12	0	0
T139	0	8	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1884	0	0
T22	864424	207	0	0
T23	92653	0	0	0
T24	623921	0	0	0
T25	0	39	0	0
T28	756654	0	0	0
T29	135458	0	0	0
T39	145962	0	0	0
T40	21887	0	0	0
T41	339108	0	0	0
T51	1108	0	0	0
T84	167583	0	0	0
T90	0	13	0	0
T107	0	76	0	0
T132	0	6	0	0
T133	0	8	0	0
T135	0	412	0	0
T136	0	30	0	0
T137	0	7	0	0
T139	0	8	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1984	0	0
T22	864424	124	0	0
T23	92653	0	0	0
T24	623921	0	0	0
T25	0	61	0	0
T28	756654	0	0	0
T29	135458	0	0	0
T39	145962	0	0	0
T40	21887	0	0	0
T41	339108	0	0	0
T51	1108	0	0	0
T84	167583	0	0	0
T90	0	19	0	0
T91	0	19	0	0
T107	0	71	0	0
T132	0	4	0	0
T133	0	2	0	0
T135	0	453	0	0
T136	0	24	0	0
T137	0	56	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2069	0	0
T22	864424	207	0	0
T23	92653	0	0	0
T24	623921	0	0	0
T25	0	55	0	0
T28	756654	0	0	0
T29	135458	0	0	0
T39	145962	0	0	0
T40	21887	0	0	0
T41	339108	0	0	0
T51	1108	0	0	0
T84	167583	0	0	0
T90	0	17	0	0
T91	0	5	0	0
T107	0	81	0	0
T132	0	1	0	0
T133	0	2	0	0
T135	0	450	0	0
T136	0	43	0	0
T137	0	24	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2068	0	0
T22	864424	167	0	0
T23	92653	0	0	0
T24	623921	0	0	0
T25	0	35	0	0
T28	756654	0	0	0
T29	135458	0	0	0
T39	145962	0	0	0
T40	21887	0	0	0
T41	339108	0	0	0
T51	1108	0	0	0
T84	167583	0	0	0
T90	0	19	0	0
T91	0	20	0	0
T107	0	69	0	0
T132	0	3	0	0
T133	0	8	0	0
T135	0	450	0	0
T136	0	47	0	0
T137	0	17	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2003	0	0
T22	864424	154	0	0
T23	92653	0	0	0
T24	623921	0	0	0
T25	0	70	0	0
T28	756654	0	0	0
T29	135458	0	0	0
T39	145962	0	0	0
T40	21887	0	0	0
T41	339108	0	0	0
T51	1108	0	0	0
T84	167583	0	0	0
T90	0	19	0	0
T91	0	10	0	0
T107	0	93	0	0
T132	0	3	0	0
T133	0	8	0	0
T135	0	437	0	0
T136	0	30	0	0
T137	0	32	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2002	0	0
T22	864424	211	0	0
T23	92653	0	0	0
T24	623921	0	0	0
T25	0	30	0	0
T28	756654	0	0	0
T29	135458	0	0	0
T39	145962	0	0	0
T40	21887	0	0	0
T41	339108	0	0	0
T51	1108	0	0	0
T84	167583	0	0	0
T90	0	21	0	0
T91	0	5	0	0
T107	0	70	0	0
T132	0	4	0	0
T133	0	8	0	0
T135	0	488	0	0
T136	0	36	0	0
T137	0	18	0	0