Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	253714902	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

202574695

1

T1

183890

T2

171

T3

100138

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	240211475	1			T1	236883		T2	100		T3	128559
values[0x0]	103810910	1			T1	106748		T2	49		T3	555513
values[0x1]	112267212	1			T1	116011		T2	44		T3	606074

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	197678082	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

258611515

1

T1

244094

T2

175

T3

132122

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1320465	1			T3	6918		T4	24		T14	1834
valid_sources[0x01]	1973191	1			T3	11524		T4	24		T14	1804
valid_sources[0x02]	1435689	1			T2	1		T3	9096		T4	23
valid_sources[0x03]	1993667	1			T3	11312		T4	21		T14	1786
valid_sources[0x04]	1316519	1			T2	2		T3	9880		T4	18
valid_sources[0x05]	2176529	1			T3	7609		T4	29		T14	1883
valid_sources[0x06]	1423370	1			T3	9216		T4	21		T14	1781
valid_sources[0x07]	1311832	1			T2	1		T3	9689		T4	23
valid_sources[0x08]	3731632	1			T2	1		T3	7879		T4	22
valid_sources[0x09]	1311421	1			T3	8813		T4	11		T14	1788
valid_sources[0x0a]	1314115	1			T3	9960		T4	21		T14	1793
valid_sources[0x0b]	1318332	1			T3	8214		T4	27		T14	1816
valid_sources[0x0c]	1322179	1			T3	9854		T4	27		T14	1850
valid_sources[0x0d]	2389420	1			T3	9646		T4	21		T14	1812
valid_sources[0x0e]	1317935	1			T2	4		T3	11176		T4	17
valid_sources[0x0f]	3093705	1			T2	1		T3	9786		T4	18
valid_sources[0x10]	1327962	1			T2	4		T3	7462		T4	21
valid_sources[0x11]	1318531	1			T2	2		T3	9488		T4	18
valid_sources[0x12]	1316524	1			T3	10623		T4	24		T14	1814
valid_sources[0x13]	1313783	1			T2	1		T3	9378		T4	21
valid_sources[0x14]	2006122	1			T3	9749		T4	21		T14	1849
valid_sources[0x15]	1317771	1			T3	11312		T4	23		T14	1802
valid_sources[0x16]	1324177	1			T3	11981		T4	15		T14	1780
valid_sources[0x17]	1311846	1			T2	1		T3	8674		T4	20
valid_sources[0x18]	4381869	1			T3	10705		T4	26		T14	1769
valid_sources[0x19]	1407399	1			T3	11285		T4	25		T14	1809
valid_sources[0x1a]	1366044	1			T3	10166		T4	21		T14	1837
valid_sources[0x1b]	2298573	1			T3	7959		T4	24		T14	1826
valid_sources[0x1c]	1384287	1			T3	7805		T4	22		T14	1933
valid_sources[0x1d]	1415783	1			T3	9969		T4	23		T14	1787
valid_sources[0x1e]	1988374	1			T3	9466		T4	21		T14	1831
valid_sources[0x1f]	1314140	1			T2	3		T3	9251		T4	20
valid_sources[0x20]	1313036	1			T3	11066		T4	17		T14	1884
valid_sources[0x21]	3371358	1			T2	1		T3	13788		T4	20
valid_sources[0x22]	1312630	1			T2	5		T3	8487		T4	19
valid_sources[0x23]	1319629	1			T2	1		T3	9072		T4	21
valid_sources[0x24]	1316249	1			T3	8507		T4	22		T14	1755
valid_sources[0x25]	1359166	1			T2	1		T3	8613		T4	25
valid_sources[0x26]	1318720	1			T2	1		T3	9270		T4	21
valid_sources[0x27]	1319296	1			T2	2		T3	8210		T4	19
valid_sources[0x28]	1369543	1			T2	4		T3	8546		T4	28
valid_sources[0x29]	2184570	1			T2	2		T3	9544		T4	31
valid_sources[0x2a]	1781736	1			T3	10383		T4	25		T14	1799
valid_sources[0x2b]	1315536	1			T3	9534		T4	26		T14	1826
valid_sources[0x2c]	4223728	1			T1	459642		T3	9582		T4	28
valid_sources[0x2d]	3740337	1			T2	4		T3	8601		T4	32
valid_sources[0x2e]	1321450	1			T3	9749		T4	27		T14	1853
valid_sources[0x2f]	1318181	1			T2	2		T3	9324		T4	31
valid_sources[0x30]	1308281	1			T3	8481		T4	22		T14	1754
valid_sources[0x31]	1450814	1			T3	10882		T4	24		T14	1809
valid_sources[0x32]	1407018	1			T2	2		T3	10460		T4	23
valid_sources[0x33]	3750593	1			T3	8510		T4	21		T14	1787
valid_sources[0x34]	1331866	1			T2	1		T3	8526		T4	26
valid_sources[0x35]	1369972	1			T2	1		T3	8199		T4	29
valid_sources[0x36]	1361711	1			T2	2		T3	8835		T4	18
valid_sources[0x37]	1359048	1			T3	12059		T4	26		T14	1844
valid_sources[0x38]	3725976	1			T2	2		T3	9737		T4	15
valid_sources[0x39]	1317731	1			T3	9058		T4	18		T14	1991
valid_sources[0x3a]	1314885	1			T3	10684		T4	26		T14	1813
valid_sources[0x3b]	1420778	1			T2	1		T3	9811		T4	21
valid_sources[0x3c]	1312408	1			T2	3		T3	7456		T4	15
valid_sources[0x3d]	1329316	1			T3	9013		T4	29		T14	1810
valid_sources[0x3e]	1977891	1			T3	9176		T4	19		T14	1830
valid_sources[0x3f]	1522234	1			T2	2		T3	11181		T4	25
valid_sources[0x40]	1313994	1			T3	9618		T4	17		T14	1806
valid_sources[0x41]	1309249	1			T3	9506		T4	22		T14	1797
valid_sources[0x42]	2876626	1			T3	7790		T4	29		T14	1879
valid_sources[0x43]	1319172	1			T2	1		T3	8320		T4	20
valid_sources[0x44]	1312586	1			T3	9486		T4	18		T14	1801
valid_sources[0x45]	1318101	1			T3	9751		T4	24		T14	1824
valid_sources[0x46]	1530494	1			T2	1		T3	7371		T4	16
valid_sources[0x47]	1309386	1			T2	4		T3	9712		T4	32
valid_sources[0x48]	1320597	1			T3	10739		T4	17		T14	1857
valid_sources[0x49]	1310775	1			T3	7153		T4	20		T14	1850
valid_sources[0x4a]	1315400	1			T3	8075		T4	15		T14	1846
valid_sources[0x4b]	2230659	1			T3	10191		T4	29		T14	1767
valid_sources[0x4c]	1315056	1			T2	1		T3	10049		T4	31
valid_sources[0x4d]	1322061	1			T3	10061		T4	26		T14	1795
valid_sources[0x4e]	1412971	1			T3	8853		T4	33		T14	1957
valid_sources[0x4f]	1315647	1			T3	12117		T4	18		T14	1880
valid_sources[0x50]	1314227	1			T3	11678		T4	16		T14	1860
valid_sources[0x51]	4646813	1			T3	8028		T4	13		T14	1815
valid_sources[0x52]	1312167	1			T3	8205		T4	26		T14	1766
valid_sources[0x53]	1315801	1			T3	9814		T4	17		T14	1779
valid_sources[0x54]	1314468	1			T2	2		T3	11095		T4	26
valid_sources[0x55]	1338367	1			T3	8422		T4	30		T14	1959
valid_sources[0x56]	1335097	1			T2	3		T3	9888		T4	19
valid_sources[0x57]	2173327	1			T2	1		T3	8135		T4	22
valid_sources[0x58]	2228272	1			T3	11402		T4	30		T14	1804
valid_sources[0x59]	2245582	1			T3	9192		T4	21		T14	1895
valid_sources[0x5a]	1314553	1			T3	8836		T4	27		T14	1860
valid_sources[0x5b]	2232184	1			T2	1		T3	7114		T4	25
valid_sources[0x5c]	1311547	1			T3	10667		T4	8		T14	1842
valid_sources[0x5d]	1984788	1			T3	8404		T4	20		T14	1915
valid_sources[0x5e]	1316617	1			T3	10085		T4	27		T14	1874
valid_sources[0x5f]	1315584	1			T3	9641		T4	20		T14	1887
valid_sources[0x60]	2194924	1			T3	10701		T4	20		T14	1796
valid_sources[0x61]	1322848	1			T2	3		T3	9786		T4	30
valid_sources[0x62]	1310124	1			T3	9492		T4	29		T14	1793
valid_sources[0x63]	1963643	1			T2	2		T3	10815		T4	17
valid_sources[0x64]	3855944	1			T2	2		T3	9446		T4	21
valid_sources[0x65]	1318323	1			T3	11264		T4	18		T14	2038
valid_sources[0x66]	1310596	1			T3	5350		T4	21		T14	1836
valid_sources[0x67]	2434817	1			T3	7630		T4	22		T14	1906
valid_sources[0x68]	4262385	1			T3	7876		T4	23		T14	1722
valid_sources[0x69]	1317013	1			T3	11808		T4	26		T14	1789
valid_sources[0x6a]	1339249	1			T3	11179		T4	15		T14	1781
valid_sources[0x6b]	1320873	1			T3	6717		T4	25		T14	1858
valid_sources[0x6c]	3246423	1			T2	2		T3	12059		T4	24
valid_sources[0x6d]	1988917	1			T3	10839		T4	30		T14	1802
valid_sources[0x6e]	2524906	1			T2	1		T3	8947		T4	24
valid_sources[0x6f]	1316098	1			T3	9713		T4	20		T14	1820
valid_sources[0x70]	1322771	1			T3	8944		T4	20		T14	1910
valid_sources[0x71]	1314710	1			T3	8880		T4	15		T14	1868
valid_sources[0x72]	1319890	1			T2	4		T3	9550		T4	21
valid_sources[0x73]	1770515	1			T3	12002		T4	20		T14	1917
valid_sources[0x74]	1346982	1			T2	1		T3	12954		T4	26
valid_sources[0x75]	1315969	1			T3	10597		T4	29		T14	1919
valid_sources[0x76]	2574526	1			T3	10857		T4	33		T14	1810
valid_sources[0x77]	1318806	1			T2	2		T3	8884		T4	15
valid_sources[0x78]	1353055	1			T3	9099		T4	20		T14	1892
valid_sources[0x79]	1319314	1			T3	8922		T4	20		T14	1851
valid_sources[0x7a]	3736730	1			T3	8867		T4	18		T14	1786
valid_sources[0x7b]	1318339	1			T3	8907		T4	18		T14	1828
valid_sources[0x7c]	1422006	1			T3	9084		T4	26		T14	1838
valid_sources[0x7d]	1344675	1			T3	10791		T4	30		T14	1791
valid_sources[0x7e]	2188480	1			T3	9899		T4	17		T14	1803
valid_sources[0x7f]	2215404	1			T3	9762		T4	11		T14	1856
valid_sources[0x80]	2274576	1			T3	9870		T4	25		T14	1793

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

87918883

1

T1

71441

T2

90

T3

429966

values[0x0]

all_enables

biggest_size

61591001

1

T1

60673

T2

44

T3

310415

values[0x1]

all_enables

biggest_size

53064811

1

T1

51776

T2

37

T3

261001