Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

256425180

1

T1

275752

T2

22

T3

144580

full_word

202746037

1

T1

183890

T2

171

T3

100138

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	459170947	1			T1	459642		T2	193		T3	244718
auto[TlIntgErrCmd]	88	1			T115	6		T116	3		T117	5
auto[TlIntgErrData]	88	1			T115	9		T116	4		T117	4
auto[TlIntgErrBoth]	94	1			T115	5		T116	3		T117	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

240742874

1

T1

236883

T2

100

T3

128559

auto[1]

218428343

1

T1

222759

T2

93

T3

116158

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	152780507	1			T1	165442		T2	10		T3	855632
auto[TlIntgErrNone]	partial	auto[1]	103644428	1			T1	110310		T2	12		T3	590171
auto[TlIntgErrNone]	full_word	auto[0]	87962245	1			T1	71441		T2	90		T3	429966
auto[TlIntgErrNone]	full_word	auto[1]	114783767	1			T1	112449		T2	81		T3	571416
auto[TlIntgErrCmd]	partial	auto[0]	34	1			T115	3		T117	2		T183	1
auto[TlIntgErrCmd]	partial	auto[1]	46	1			T115	2		T116	3		T117	2
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T190	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T115	1		T117	1		T188	1
auto[TlIntgErrData]	partial	auto[0]	45	1			T115	4		T116	1		T117	2
auto[TlIntgErrData]	partial	auto[1]	35	1			T115	4		T116	3		T117	2
auto[TlIntgErrData]	full_word	auto[0]	4	1			T188	1		T186	1		T191	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T115	1		T183	1		T192	1
auto[TlIntgErrBoth]	partial	auto[0]	34	1			T115	1		T116	1		T189	1
auto[TlIntgErrBoth]	partial	auto[1]	51	1			T115	2		T116	1		T189	3
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T115	2		T189	1		T191	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T116	1		T117	1		T191	1