Module Definition
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Module : prim_packer
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.50 100.00 100.00 90.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_msgfifo.u_packer 97.50 100.00 100.00 90.00 100.00



Module Instance : tb.dut.u_msgfifo.u_packer

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.50 100.00 100.00 90.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.50 100.00 100.00 90.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.92 100.00 100.00 91.67 100.00 u_msgfifo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : prim_packer
Line No.TotalCoveredPercent
TOTAL6666100.00
ALWAYS6533100.00
CONT_ASSIGN7211100.00
ALWAYS7866100.00
ALWAYS9055100.00
ALWAYS15744100.00
CONT_ASSIGN16511100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN17011100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN17411100.00
CONT_ASSIGN17511100.00
CONT_ASSIGN17811100.00
CONT_ASSIGN18011100.00
ALWAYS18599100.00
ALWAYS21488100.00
ALWAYS23533100.00
ALWAYS2431414100.00
CONT_ASSIGN27911100.00
CONT_ASSIGN28311100.00
CONT_ASSIGN29100
CONT_ASSIGN29411100.00
CONT_ASSIGN29511100.00
CONT_ASSIGN29611100.00
CONT_ASSIGN29900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 1 1
66 1 1
67 1 1
72 1 1
78 1 1
80 1 1
81 1 1
82 1 1
83 1 1
84 1 1
90 1 1
91 1 1
92 1 1
93 1 1
95 1 1
157 1 1
158 1 1
159 1 1
160 1 1
MISSING_ELSE
165 1 1
166 1 1
170 1 1
171 1 1
174 1 1
175 1 1
178 1 1
180 1 1
185 1 1
187 1 1
188 1 1
192 1 1
193 1 1
197 1 1
198 1 1
202 1 1
203 1 1
214 1 1
215 1 1
216 1 1
217 1 1
218 1 1
219 1 1
221 1 1
222 1 1
235 1 1
236 1 1
238 1 1
243 1 1
245 1 1
246 1 1
248 1 1
250 1 1
251 1 1
253 1 1
258 1 1
259 1 1
261 1 1
262 1 1
264 1 1
266 1 1
267 1 1
279 1 1
283 1 1
291 unreachable
294 1 1
295 1 1
296 1 1
299 unreachable


Cond Coverage for Module : prim_packer
TotalCoveredPercent
Conditions1616100.00
Logical1616100.00
Non-Logical00
Event00

 LINE       82
 EXPRESSION ((int'(pos_q) <= OutW) ? '0 : ((pos_q - 8'(OutW))))
             ----------1----------
-1-StatusTests
0UnreachableT1,T2,T3
1CoveredT1,T3,T4

 LINE       84
 EXPRESSION ((int'(pos_with_input) <= OutW) ? '0 : ((pos_with_input - 8'(OutW))))
             ---------------1--------------
-1-StatusTests
0UnreachableT15,T16,T21
1CoveredT16,T26,T103

 LINE       159
 EXPRESSION (mask_i[i] == 1'b1)
            ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       165
 EXPRESSION (valid_i & ready_o)
             ---1---   ---2---
-1--2-StatusTests
01CoveredT1,T2,T3
10UnreachableT16,T21,T25
11CoveredT1,T2,T3

 LINE       166
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT16,T21,T25
11CoveredT1,T2,T3

 LINE       170
 EXPRESSION (valid_i ? ((data_i >> lod_idx)) : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       171
 EXPRESSION (valid_i ? ((mask_i >> lod_idx)) : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       258
 EXPRESSION (pos_q == '0)
            ------1------
-1-StatusTests
0CoveredT1,T3,T4
1CoveredT1,T3,T4

 LINE       283
 EXPRESSION ((int'(pos_q) >= OutW) ? 1'b1 : flush_valid)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1UnreachableT1,T2,T3

Branch Coverage for Module : prim_packer
Line No.TotalCoveredPercent
Branches 30 27 90.00
TERNARY 170 2 2 100.00
TERNARY 171 2 2 100.00
TERNARY 283 1 1 100.00
IF 159 2 2 100.00
CASE 185 5 4 80.00
IF 214 3 3 100.00
IF 235 2 2 100.00
CASE 248 5 4 80.00
CASE 80 5 4 80.00
IF 90 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 170 (valid_i) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 171 (valid_i) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 283 ((int'(pos_q) >= OutW)) ?

Branches:
-1-StatusTests
1 Unreachable T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 159 if ((mask_i[i] == 1'b1))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 185 case ({ack_in, ack_out})

Branches:
-1-StatusTests
2'b00 Covered T1,T2,T3
2'b01 Covered T1,T2,T3
2'b10 Covered T1,T2,T3
2'b11 Covered T15,T16,T21
default Not Covered


LineNo. Expression -1-: 214 if ((!rst_ni)) -2-: 217 if (flush_done)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T3,T4
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 235 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 248 case (flush_st) -2-: 250 if (flush_i) -3-: 258 if ((pos_q == '0))

Branches:
-1--2--3-StatusTests
FlushIdle 1 - Covered T1,T3,T4
FlushIdle 0 - Covered T1,T2,T3
FlushSend - 1 Covered T1,T3,T4
FlushSend - 0 Covered T1,T3,T4
default - - Not Covered


LineNo. Expression -1-: 80 case ({ack_in, ack_out}) -2-: 82 ((int'(pos_q) <= OutW)) ? -3-: 84 ((int'(pos_with_input) <= OutW)) ?

Branches:
-1--2--3-StatusTests
2'b00 - - Covered T1,T2,T3
2'b01 1 - Covered T1,T3,T4
2'b01 0 - Unreachable T1,T2,T3
2'b10 - - Covered T1,T2,T3
2'b11 - 1 Covered T16,T26,T103
2'b11 - 0 Unreachable T15,T16,T21
default - - Not Covered


LineNo. Expression -1-: 90 if ((!rst_ni)) -2-: 92 if (flush_done)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T3,T4
0 0 Covered T1,T2,T3


Assert Coverage for Module : prim_packer
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 28 28 100.00 28 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 28 28 100.00 28 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataIStable_M 2147483647 118094 0 1032
DataOStableWhenPending_A 2147483647 96565 0 1032
ExFlushValid_M 2147483647 350300 0 0
ExcessiveDataStored_A 2147483647 52746 0 0
ExcessiveMaskStored_A 2147483647 52746 0 0
FlushFollowedByDone_A 2147483647 350300 0 1032
ValidIDeassertedOnFlush_M 2147483647 553714 0 0
ValidOAssertedForStoredDataGTEOutW_A 2147483647 48464892 0 0
ValidOPairedWidthReadyI_A 2147483647 96565 0 0
g_byte_assert.InputDividedBy8_A 1032 1032 0 0
g_byte_assert.OutputDividedBy8_A 1032 1032 0 0
g_byte_assert.g_byte_input_masking[0].InputMaskContiguous_A 2147483647 110585345 0 0
g_byte_assert.g_byte_input_masking[1].InputMaskContiguous_A 2147483647 110585345 0 0
g_byte_assert.g_byte_input_masking[2].InputMaskContiguous_A 2147483647 110585345 0 0
g_byte_assert.g_byte_input_masking[3].InputMaskContiguous_A 2147483647 110585345 0 0
g_byte_assert.g_byte_input_masking[4].InputMaskContiguous_A 2147483647 110585345 0 0
g_byte_assert.g_byte_input_masking[5].InputMaskContiguous_A 2147483647 110585345 0 0
g_byte_assert.g_byte_input_masking[6].InputMaskContiguous_A 2147483647 110585345 0 0
g_byte_assert.g_byte_input_masking[7].InputMaskContiguous_A 2147483647 110585345 0 0
g_byte_assert.g_byte_output_masking[0].OutputMaskContiguous_A 2147483647 48666216 0 0
g_byte_assert.g_byte_output_masking[1].OutputMaskContiguous_A 2147483647 48666216 0 0
g_byte_assert.g_byte_output_masking[2].OutputMaskContiguous_A 2147483647 48666216 0 0
g_byte_assert.g_byte_output_masking[3].OutputMaskContiguous_A 2147483647 48666216 0 0
g_byte_assert.g_byte_output_masking[4].OutputMaskContiguous_A 2147483647 48666216 0 0
g_byte_assert.g_byte_output_masking[5].OutputMaskContiguous_A 2147483647 48666216 0 0
g_byte_assert.g_byte_output_masking[6].OutputMaskContiguous_A 2147483647 48666216 0 0
g_byte_assert.g_byte_output_masking[7].OutputMaskContiguous_A 2147483647 48666216 0 0
gen_mask_assert.ContiguousOnesMask_M 2147483647 110585345 0 0


DataIStable_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 118094 0 1032
T16 191476 1213 0 1
T17 101559 0 0 1
T18 265303 0 0 1
T19 6178 0 0 1
T21 22639 85 0 1
T23 0 5 0 0
T24 0 6 0 0
T25 483117 3126 0 1
T26 0 597 0 0
T30 0 386 0 0
T38 2661 0 0 1
T39 17337 0 0 1
T40 129784 0 0 1
T41 287583 0 0 1
T53 0 598 0 0
T103 0 236 0 0
T104 0 267 0 0

DataOStableWhenPending_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 96565 0 1032
T5 0 33 0 0
T16 191476 232 0 1
T17 101559 0 0 1
T18 265303 0 0 1
T19 6178 0 0 1
T21 22639 85 0 1
T25 483117 3277 0 1
T26 0 118 0 0
T30 0 386 0 0
T38 2661 0 0 1
T39 17337 0 0 1
T40 129784 0 0 1
T41 287583 0 0 1
T53 0 94 0 0
T75 0 470 0 0
T103 0 57 0 0
T104 0 267 0 0

ExFlushValid_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 350300 0 0
T1 945066 246 0 0
T2 3922 0 0 0
T3 514200 2337 0 0
T4 203288 82 0 0
T13 83880 11 0 0
T14 965561 246 0 0
T15 154500 192 0 0
T16 191476 198 0 0
T17 101559 18 0 0
T18 265303 194 0 0
T19 0 9 0 0

ExcessiveDataStored_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 52746 0 0
T15 154500 25 0 0
T16 191476 371 0 0
T17 101559 0 0 0
T18 265303 0 0 0
T19 6178 0 0 0
T21 22639 53 0 0
T22 0 10 0 0
T23 0 3 0 0
T25 0 1431 0 0
T26 0 196 0 0
T27 0 2 0 0
T28 0 5 0 0
T38 2661 0 0 0
T39 17337 0 0 0
T40 129784 0 0 0
T41 287583 0 0 0
T103 0 79 0 0

ExcessiveMaskStored_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 52746 0 0
T15 154500 25 0 0
T16 191476 371 0 0
T17 101559 0 0 0
T18 265303 0 0 0
T19 6178 0 0 0
T21 22639 53 0 0
T22 0 10 0 0
T23 0 3 0 0
T25 0 1431 0 0
T26 0 196 0 0
T27 0 2 0 0
T28 0 5 0 0
T38 2661 0 0 0
T39 17337 0 0 0
T40 129784 0 0 0
T41 287583 0 0 0
T103 0 79 0 0

FlushFollowedByDone_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 350300 0 1032
T1 945066 246 0 1
T2 3922 0 0 1
T3 514200 2337 0 1
T4 203288 82 0 1
T13 83880 11 0 1
T14 965561 246 0 1
T15 154500 192 0 1
T16 191476 198 0 1
T17 101559 18 0 1
T18 265303 194 0 1
T19 0 9 0 0

ValidIDeassertedOnFlush_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 553714 0 0
T1 945066 460 0 0
T2 3922 0 0 0
T3 514200 3395 0 0
T4 203288 152 0 0
T13 83880 11 0 0
T14 965561 460 0 0
T15 154500 346 0 0
T16 191476 366 0 0
T17 101559 18 0 0
T18 265303 365 0 0
T19 0 18 0 0

ValidOAssertedForStoredDataGTEOutW_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 48464892 0 0
T1 945066 47532 0 0
T2 3922 1 0 0
T3 514200 240518 0 0
T4 203288 5596 0 0
T13 83880 0 0 0
T14 965561 47532 0 0
T15 154500 11725 0 0
T16 191476 12897 0 0
T17 101559 0 0 0
T18 265303 126274 0 0
T19 0 100 0 0
T39 0 100 0 0

ValidOPairedWidthReadyI_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 96565 0 0
T5 0 33 0 0
T16 191476 232 0 0
T17 101559 0 0 0
T18 265303 0 0 0
T19 6178 0 0 0
T21 22639 85 0 0
T25 483117 3277 0 0
T26 0 118 0 0
T30 0 386 0 0
T38 2661 0 0 0
T39 17337 0 0 0
T40 129784 0 0 0
T41 287583 0 0 0
T53 0 94 0 0
T75 0 470 0 0
T103 0 57 0 0
T104 0 267 0 0

g_byte_assert.InputDividedBy8_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1032 1032 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

g_byte_assert.OutputDividedBy8_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1032 1032 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

g_byte_assert.g_byte_input_masking[0].InputMaskContiguous_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 110585345 0 0
T1 945066 109831 0 0
T2 3922 4 0 0
T3 514200 566082 0 0
T4 203288 13252 0 0
T13 83880 0 0 0
T14 965561 112445 0 0
T15 154500 22761 0 0
T16 191476 31121 0 0
T17 101559 0 0 0
T18 265303 299224 0 0
T19 0 247 0 0
T39 0 261 0 0

g_byte_assert.g_byte_input_masking[1].InputMaskContiguous_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 110585345 0 0
T1 945066 109831 0 0
T2 3922 4 0 0
T3 514200 566082 0 0
T4 203288 13252 0 0
T13 83880 0 0 0
T14 965561 112445 0 0
T15 154500 22761 0 0
T16 191476 31121 0 0
T17 101559 0 0 0
T18 265303 299224 0 0
T19 0 247 0 0
T39 0 261 0 0

g_byte_assert.g_byte_input_masking[2].InputMaskContiguous_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 110585345 0 0
T1 945066 109831 0 0
T2 3922 4 0 0
T3 514200 566082 0 0
T4 203288 13252 0 0
T13 83880 0 0 0
T14 965561 112445 0 0
T15 154500 22761 0 0
T16 191476 31121 0 0
T17 101559 0 0 0
T18 265303 299224 0 0
T19 0 247 0 0
T39 0 261 0 0

g_byte_assert.g_byte_input_masking[3].InputMaskContiguous_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 110585345 0 0
T1 945066 109831 0 0
T2 3922 4 0 0
T3 514200 566082 0 0
T4 203288 13252 0 0
T13 83880 0 0 0
T14 965561 112445 0 0
T15 154500 22761 0 0
T16 191476 31121 0 0
T17 101559 0 0 0
T18 265303 299224 0 0
T19 0 247 0 0
T39 0 261 0 0

g_byte_assert.g_byte_input_masking[4].InputMaskContiguous_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 110585345 0 0
T1 945066 109831 0 0
T2 3922 4 0 0
T3 514200 566082 0 0
T4 203288 13252 0 0
T13 83880 0 0 0
T14 965561 112445 0 0
T15 154500 22761 0 0
T16 191476 31121 0 0
T17 101559 0 0 0
T18 265303 299224 0 0
T19 0 247 0 0
T39 0 261 0 0

g_byte_assert.g_byte_input_masking[5].InputMaskContiguous_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 110585345 0 0
T1 945066 109831 0 0
T2 3922 4 0 0
T3 514200 566082 0 0
T4 203288 13252 0 0
T13 83880 0 0 0
T14 965561 112445 0 0
T15 154500 22761 0 0
T16 191476 31121 0 0
T17 101559 0 0 0
T18 265303 299224 0 0
T19 0 247 0 0
T39 0 261 0 0

g_byte_assert.g_byte_input_masking[6].InputMaskContiguous_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 110585345 0 0
T1 945066 109831 0 0
T2 3922 4 0 0
T3 514200 566082 0 0
T4 203288 13252 0 0
T13 83880 0 0 0
T14 965561 112445 0 0
T15 154500 22761 0 0
T16 191476 31121 0 0
T17 101559 0 0 0
T18 265303 299224 0 0
T19 0 247 0 0
T39 0 261 0 0

g_byte_assert.g_byte_input_masking[7].InputMaskContiguous_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 110585345 0 0
T1 945066 109831 0 0
T2 3922 4 0 0
T3 514200 566082 0 0
T4 203288 13252 0 0
T13 83880 0 0 0
T14 965561 112445 0 0
T15 154500 22761 0 0
T16 191476 31121 0 0
T17 101559 0 0 0
T18 265303 299224 0 0
T19 0 247 0 0
T39 0 261 0 0

g_byte_assert.g_byte_output_masking[0].OutputMaskContiguous_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 48666216 0 0
T1 945066 47746 0 0
T2 3922 1 0 0
T3 514200 241576 0 0
T4 203288 5666 0 0
T13 83880 0 0 0
T14 965561 47746 0 0
T15 154500 11879 0 0
T16 191476 13065 0 0
T17 101559 0 0 0
T18 265303 126445 0 0
T19 0 109 0 0
T39 0 109 0 0

g_byte_assert.g_byte_output_masking[1].OutputMaskContiguous_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 48666216 0 0
T1 945066 47746 0 0
T2 3922 1 0 0
T3 514200 241576 0 0
T4 203288 5666 0 0
T13 83880 0 0 0
T14 965561 47746 0 0
T15 154500 11879 0 0
T16 191476 13065 0 0
T17 101559 0 0 0
T18 265303 126445 0 0
T19 0 109 0 0
T39 0 109 0 0

g_byte_assert.g_byte_output_masking[2].OutputMaskContiguous_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 48666216 0 0
T1 945066 47746 0 0
T2 3922 1 0 0
T3 514200 241576 0 0
T4 203288 5666 0 0
T13 83880 0 0 0
T14 965561 47746 0 0
T15 154500 11879 0 0
T16 191476 13065 0 0
T17 101559 0 0 0
T18 265303 126445 0 0
T19 0 109 0 0
T39 0 109 0 0

g_byte_assert.g_byte_output_masking[3].OutputMaskContiguous_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 48666216 0 0
T1 945066 47746 0 0
T2 3922 1 0 0
T3 514200 241576 0 0
T4 203288 5666 0 0
T13 83880 0 0 0
T14 965561 47746 0 0
T15 154500 11879 0 0
T16 191476 13065 0 0
T17 101559 0 0 0
T18 265303 126445 0 0
T19 0 109 0 0
T39 0 109 0 0

g_byte_assert.g_byte_output_masking[4].OutputMaskContiguous_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 48666216 0 0
T1 945066 47746 0 0
T2 3922 1 0 0
T3 514200 241576 0 0
T4 203288 5666 0 0
T13 83880 0 0 0
T14 965561 47746 0 0
T15 154500 11879 0 0
T16 191476 13065 0 0
T17 101559 0 0 0
T18 265303 126445 0 0
T19 0 109 0 0
T39 0 109 0 0

g_byte_assert.g_byte_output_masking[5].OutputMaskContiguous_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 48666216 0 0
T1 945066 47746 0 0
T2 3922 1 0 0
T3 514200 241576 0 0
T4 203288 5666 0 0
T13 83880 0 0 0
T14 965561 47746 0 0
T15 154500 11879 0 0
T16 191476 13065 0 0
T17 101559 0 0 0
T18 265303 126445 0 0
T19 0 109 0 0
T39 0 109 0 0

g_byte_assert.g_byte_output_masking[6].OutputMaskContiguous_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 48666216 0 0
T1 945066 47746 0 0
T2 3922 1 0 0
T3 514200 241576 0 0
T4 203288 5666 0 0
T13 83880 0 0 0
T14 965561 47746 0 0
T15 154500 11879 0 0
T16 191476 13065 0 0
T17 101559 0 0 0
T18 265303 126445 0 0
T19 0 109 0 0
T39 0 109 0 0

g_byte_assert.g_byte_output_masking[7].OutputMaskContiguous_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 48666216 0 0
T1 945066 47746 0 0
T2 3922 1 0 0
T3 514200 241576 0 0
T4 203288 5666 0 0
T13 83880 0 0 0
T14 965561 47746 0 0
T15 154500 11879 0 0
T16 191476 13065 0 0
T17 101559 0 0 0
T18 265303 126445 0 0
T19 0 109 0 0
T39 0 109 0 0

gen_mask_assert.ContiguousOnesMask_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 110585345 0 0
T1 945066 109831 0 0
T2 3922 4 0 0
T3 514200 566082 0 0
T4 203288 13252 0 0
T13 83880 0 0 0
T14 965561 112445 0 0
T15 154500 22761 0 0
T16 191476 31121 0 0
T17 101559 0 0 0
T18 265303 299224 0 0
T19 0 247 0 0
T39 0 261 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%