Unified Coverage Report :: Module :: kmac_core

Module : kmac_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.80	100.00	100.00		100.00	94.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_kmac_core	98.80	100.00	100.00		100.00	94.00	100.00

---

Module Instance : tb.dut.u_kmac_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.80	100.00	100.00		100.00	94.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.04	100.00	100.00	100.00	100.00	94.23	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_key_slicer[0].u_key_slicer	100.00	100.00					100.00
u_key_index_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : kmac_core

	Line No.	Total	Covered	Percent
TOTAL		69	69	100.00
CONT_ASSIGN	153	1	1	100.00
ALWAYS	161	3	3	100.00
ALWAYS	166	30	30	100.00
CONT_ASSIGN	251	1	1	100.00
CONT_ASSIGN	252	1	1	100.00
CONT_ASSIGN	253	1	1	100.00
CONT_ASSIGN	254	1	1	100.00
CONT_ASSIGN	258	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
ALWAYS	268	6	6	100.00
CONT_ASSIGN	287	1	1	100.00
ALWAYS	307	6	6	100.00
ALWAYS	338	6	6	100.00
CONT_ASSIGN	372	1	1	100.00
CONT_ASSIGN	394	1	1	100.00
ALWAYS	420	6	6	100.00
CONT_ASSIGN	431	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
153	1	1
161	3	3
166	1	1
168	1	1
169	1	1
171	1	1
173	1	1
174	1	1
176	1	1
178	1	1
180	1	1
181	1	1
183	1	1
190	1	1
191	1	1
193	1	1
194	1	1
196	1	1
197	1	1
199	1	1
201	1	1
207	1	1
208	1	1
210	1	1
212	1	1
217	1	1
218	1	1
220	1	1
226	1	1
227	1	1
240	1	1
241	1	1
			MISSING_ELSE
251	1	1
252	1	1
253	1	1
254	1	1
258	1	1
260	1	1
265	1	1
268	1	1
269	1	1
270	1	1
271	1	1
272	1	1
274	1	1
			MISSING_ELSE
287	1	1
307	1	1
317	1	1
318	1	1
319	1	1
320	1	1
321	1	1
338	1	1
341	1	1
345	1	1
349	1	1
353	1	1
358	1	1
372	1	1
394	1	1
420	1	1
421	1	1
422	1	1
423	1	1
424	1	1
425	1	1
431	1	1

---

Cond Coverage for Module : kmac_core

	Total	Covered	Percent
Conditions	28	28	100.00
Logical	28	28	100.00
Non-Logical	0	0
Event	0	0

 LINE       180
 EXPRESSION (kmac_en_i && start_i)
             ----1----    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T13,T15
1	1	Covered	T4,T13,T15

 LINE       207
 EXPRESSION (process_i || process_latched)
             ----1----    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T4,T13,T15
0	1	Covered	T105
1	0	Covered	T4,T13,T15

 LINE       251
 EXPRESSION (en_kmac_datapath ? kmac_valid : fifo_valid_i)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T13,T15

 LINE       252
 EXPRESSION (en_kmac_datapath ? kmac_data : fifo_data_i)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T13,T15

 LINE       253
 EXPRESSION (en_kmac_datapath ? kmac_strb : fifo_strb_i)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T13,T15

 LINE       254
 EXPRESSION (en_kmac_datapath ? 1'b0 : msg_ready_i)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T13,T15

 LINE       258
 EXPRESSION (en_key_write ? '1 : '0)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T13,T15

 LINE       260
 EXPRESSION (en_key_write ? key_sliced : ('{(*adjust*)default:'0}))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T13,T15

 LINE       265
 EXPRESSION (kmac_en_i ? kmac_process : process_i)
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T13,T15

 LINE       270
 EXPRESSION (process_i && ((!process_o)))
             ----1----    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T105,T87

 LINE       394
 EXPRESSION (kmac_valid & msg_ready_i)
             -----1----   -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T13,T15
1	1	Covered	T4,T13,T15

 LINE       431
 EXPRESSION (key_index == block_addr_limit)
            ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T13,T15

---

FSM Coverage for Module : kmac_core

Summary for FSM :: st

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	8	8	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: st

---

states	Line No.	Covered	Tests
StKey	181	Covered	T4,T13,T15
StKmacFlush	208	Covered	T4,T13,T15
StKmacIdle	183	Covered	T1,T2,T3
StKmacMsg	194	Covered	T4,T13,T15
StTerminalError	241	Covered	T2,T5,T6

transitions	Line No.	Covered	Tests
StKey->StKmacMsg	194	Covered	T4,T13,T15
StKey->StTerminalError	241	Covered	T34,T57,T58
StKmacFlush->StKmacIdle	218	Covered	T4,T13,T15
StKmacFlush->StTerminalError	241	Covered	T54,T7,T106
StKmacIdle->StKey	181	Covered	T4,T13,T15
StKmacIdle->StTerminalError	241	Covered	T2,T5,T6
StKmacMsg->StKmacFlush	208	Covered	T4,T13,T15
StKmacMsg->StTerminalError	241	Covered	T37,T35,T107

---

Branch Coverage for Module : kmac_core

	Line No.	Total	Covered	Percent
Branches		50	47	94.00
TERNARY	251	2	2	100.00
TERNARY	252	2	2	100.00
TERNARY	253	2	2	100.00
TERNARY	254	2	2	100.00
TERNARY	258	2	2	100.00
TERNARY	260	2	2	100.00
TERNARY	265	2	2	100.00
IF	161	2	2	100.00
CASE	178	10	10	100.00
IF	240	2	2	100.00
IF	268	4	4	100.00
CASE	307	6	5	83.33
CASE	420	6	5	83.33
CASE	338	6	5	83.33

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	251	(en_kmac_datapath) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T13,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	252	(en_kmac_datapath) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T13,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	253	(en_kmac_datapath) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T13,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	254	(en_kmac_datapath) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T13,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	258	(en_key_write) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T13,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	260	(en_key_write) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T13,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	265	(kmac_en_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T13,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	161	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	178	case (st)
-2-:	180	if ((kmac_en_i && start_i))
-3-:	193	if (sent_blocksize)
-4-:	207	if ((process_i || process_latched))
-5-:	217	if (prim_mubi_pkg::mubi4_test_true_strict(done_i))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
StKmacIdle	1	-	-	-	Covered	T4,T13,T15
StKmacIdle	0	-	-	-	Covered	T1,T2,T3
StKey	-	1	-	-	Covered	T4,T13,T15
StKey	-	0	-	-	Covered	T4,T13,T15
StKmacMsg	-	-	1	-	Covered	T4,T13,T15
StKmacMsg	-	-	0	-	Covered	T4,T13,T15
StKmacFlush	-	-	-	1	Covered	T4,T13,T15
StKmacFlush	-	-	-	0	Covered	T4,T13,T15
StTerminalError	-	-	-	-	Covered	T2,T5,T6
default	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	240	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i))

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	268	if ((!rst_ni))
-2-:	270	if ((process_i && (!process_o)))
-3-:	272	if ((process_o || prim_mubi_pkg::mubi4_test_true_strict(done_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T105,T87
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	307	case (key_len_i)

Branches:

-1-	Status	Tests
Key128	Covered	T1,T2,T3
Key192	Covered	T1,T3,T13
Key256	Covered	T1,T2,T3
Key384	Covered	T1,T3,T13
Key512	Covered	T1,T3,T13
default	Not Covered

	LineNo.	Expression
-1-:	420	case (strength_i)

Branches:

-1-	Status	Tests
L128	Covered	T1,T2,T3
L224	Covered	T4,T15,T16
L256	Covered	T1,T2,T3
L384	Covered	T4,T13,T15
L512	Covered	T1,T4,T14
default	Not Covered

	LineNo.	Expression
-1-:	338	case (key_len_i)

Branches:

-1-	Status	Tests
Key128	Covered	T1,T2,T3
Key192	Covered	T1,T3,T13
Key256	Covered	T1,T2,T3
Key384	Covered	T1,T3,T13
Key512	Covered	T1,T3,T13
default	Not Covered

---

Assert Coverage for Module : kmac_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	9	9	100.00	9	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	9	9	100.00	9	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckOnlyInMessageState_A	2147483647	8368087	0	0
KeyDataStableWhenValid_M	2147483647	311521059	0	0
KeyLengthStableWhenValid_M	2147483647	311521059	0	0
KmacEnStable_M	2147483647	23194	0	0
MaxKeyLenMatchToKey512_A	1032	1032	0	0
ModeStable_M	2147483647	35068	0	0
ProcessLatchedCleared_A	2147483647	1	0	0
StrengthStable_M	2147483647	41790	0	0
u_state_regs_A	2147483647	2147483647	0	0

AckOnlyInMessageState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8368087	0	0
T4	203288	4393	0	0
T13	83880	0	0	0
T14	965561	0	0	0
T15	154500	5916	0	0
T16	191476	6385	0	0
T17	101559	0	0	0
T18	265303	104719	0	0
T19	6178	109	0	0
T21	0	84	0	0
T25	0	3296	0	0
T38	2661	0	0	0
T39	17337	109	0	0
T41	0	31743	0	0
T51	0	67127	0	0

KeyDataStableWhenValid_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	311521059	0	0
T4	203288	146294	0	0
T13	83880	0	0	0
T14	965561	0	0	0
T15	154500	683526	0	0
T16	191476	943537	0	0
T17	101559	0	0	0
T18	265303	216957	0	0
T19	6178	4400	0	0
T21	0	18183	0	0
T25	0	216255	0	0
T38	2661	0	0	0
T39	17337	12847	0	0
T41	0	205048	0	0
T51	0	134864	0	0

KeyLengthStableWhenValid_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	311521059	0	0
T4	203288	146294	0	0
T13	83880	0	0	0
T14	965561	0	0	0
T15	154500	683526	0	0
T16	191476	943537	0	0
T17	101559	0	0	0
T18	265303	216957	0	0
T19	6178	4400	0	0
T21	0	18183	0	0
T25	0	216255	0	0
T38	2661	0	0	0
T39	17337	12847	0	0
T41	0	205048	0	0
T51	0	134864	0	0

KmacEnStable_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	23194	0	0
T4	203288	33	0	0
T13	83880	20	0	0
T14	965561	0	0	0
T15	154500	98	0	0
T16	191476	102	0	0
T17	101559	23	0	0
T18	265303	67	0	0
T19	6178	1	0	0
T21	0	3	0	0
T38	2661	0	0	0
T39	17337	1	0	0
T41	0	26	0	0

MaxKeyLenMatchToKey512_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1032	1032	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

ModeStable_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	35068	0	0
T2	3922	1	0	0
T3	514200	1	0	0
T4	203288	34	0	0
T13	83880	20	0	0
T14	965561	0	0	0
T15	154500	168	0	0
T16	191476	186	0	0
T17	101559	26	0	0
T18	265303	68	0	0
T19	0	1	0	0
T38	2661	0	0	0
T39	0	1	0	0

ProcessLatchedCleared_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1	0	0
T7	3552	0	0	0
T48	341808	0	0	0
T105	68553	1	0	0
T108	6372	0	0	0
T109	6341	0	0	0
T110	177416	0	0	0
T111	255651	0	0	0
T112	925426	0	0	0
T113	78744	0	0	0
T114	23586	0	0	0

StrengthStable_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	41790	0	0
T1	945066	2	0	0
T2	3922	3	0	0
T3	514200	1	0	0
T4	203288	49	0	0
T13	83880	19	0	0
T14	965561	2	0	0
T15	154500	188	0	0
T16	191476	187	0	0
T17	101559	33	0	0
T18	265303	111	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	945066	944977	0	0
T2	3922	3779	0	0
T3	514200	514193	0	0
T4	203288	203236	0	0
T13	83880	83821	0	0
T14	965561	965499	0	0
T15	154500	154494	0	0
T16	191476	191467	0	0
T17	101559	101493	0	0
T18	265303	265296	0	0