Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	629229	0	0
entropy_period_rd_A	2147483647	2105	0	0
intr_enable_rd_A	2147483647	2793	0	0
prefix_0_rd_A	2147483647	2100	0	0
prefix_10_rd_A	2147483647	2183	0	0
prefix_1_rd_A	2147483647	2085	0	0
prefix_2_rd_A	2147483647	2305	0	0
prefix_3_rd_A	2147483647	2066	0	0
prefix_4_rd_A	2147483647	1980	0	0
prefix_5_rd_A	2147483647	2086	0	0
prefix_6_rd_A	2147483647	2049	0	0
prefix_7_rd_A	2147483647	2093	0	0
prefix_8_rd_A	2147483647	2245	0	0
prefix_9_rd_A	2147483647	2055	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	629229	0	0
T31	0	55806	0	0
T33	0	72644	0	0
T52	702573	89274	0	0
T85	0	37525	0	0
T121	0	44943	0	0
T122	0	96339	0	0
T123	0	41102	0	0
T124	0	31891	0	0
T125	0	34047	0	0
T126	0	28984	0	0
T127	151160	0	0	0
T128	133713	0	0	0
T129	511328	0	0	0
T130	7282	0	0	0
T131	916059	0	0	0
T132	112422	0	0	0
T133	642160	0	0	0
T134	860031	0	0	0
T135	541389	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2105	0	0
T89	6825	52	0	0
T95	7114	60	0	0
T116	12390	56	0	0
T146	4652	17	0	0
T147	52692	419	0	0
T148	1989	5	0	0
T149	73079	118	0	0
T150	9513	21	0	0
T151	2171	8	0	0
T152	7376	2	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2793	0	0
T89	6825	57	0	0
T146	4652	7	0	0
T147	52692	415	0	0
T148	1989	9	0	0
T149	73079	154	0	0
T150	9513	34	0	0
T151	2171	15	0	0
T152	7376	26	0	0
T153	1272	15	0	0
T154	1393	16	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2100	0	0
T89	6825	21	0	0
T95	7114	20	0	0
T116	12390	37	0	0
T146	4652	6	0	0
T147	52692	438	0	0
T148	1989	2	0	0
T149	73079	219	0	0
T150	9513	44	0	0
T151	2171	2	0	0
T152	7376	1	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2183	0	0
T89	6825	41	0	0
T92	2999	4	0	0
T95	7114	19	0	0
T116	12390	47	0	0
T146	4652	17	0	0
T147	52692	430	0	0
T148	1989	6	0	0
T149	73079	225	0	0
T150	9513	18	0	0
T152	7376	12	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2085	0	0
T89	6825	34	0	0
T95	7114	30	0	0
T116	12390	23	0	0
T146	4652	3	0	0
T147	52692	407	0	0
T148	1989	3	0	0
T149	73079	226	0	0
T150	9513	30	0	0
T151	2171	3	0	0
T152	7376	9	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2305	0	0
T89	6825	34	0	0
T95	7114	53	0	0
T116	12390	32	0	0
T146	4652	8	0	0
T147	52692	479	0	0
T148	1989	7	0	0
T149	73079	236	0	0
T150	9513	44	0	0
T151	2171	4	0	0
T152	7376	21	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2066	0	0
T89	6825	32	0	0
T95	7114	39	0	0
T116	12390	30	0	0
T146	4652	15	0	0
T147	52692	453	0	0
T148	1989	6	0	0
T149	73079	232	0	0
T150	9513	15	0	0
T151	2171	1	0	0
T152	7376	8	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1980	0	0
T89	6825	31	0	0
T95	7114	32	0	0
T116	12390	17	0	0
T146	4652	1	0	0
T147	52692	399	0	0
T148	1989	5	0	0
T149	73079	235	0	0
T150	9513	21	0	0
T151	2171	9	0	0
T152	7376	9	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2086	0	0
T89	6825	25	0	0
T92	2999	12	0	0
T95	7114	33	0	0
T116	12390	24	0	0
T146	4652	7	0	0
T147	52692	467	0	0
T149	73079	263	0	0
T150	9513	21	0	0
T151	2171	3	0	0
T152	7376	12	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2049	0	0
T89	6825	25	0	0
T95	7114	32	0	0
T116	12390	30	0	0
T146	4652	8	0	0
T147	52692	410	0	0
T148	1989	6	0	0
T149	73079	239	0	0
T150	9513	3	0	0
T151	2171	4	0	0
T152	7376	3	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2093	0	0
T89	6825	40	0	0
T92	2999	8	0	0
T95	7114	36	0	0
T116	12390	25	0	0
T146	4652	10	0	0
T147	52692	423	0	0
T149	73079	223	0	0
T150	9513	7	0	0
T151	2171	5	0	0
T152	7376	18	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2245	0	0
T89	6825	37	0	0
T95	7114	27	0	0
T116	12390	25	0	0
T146	4652	6	0	0
T147	52692	453	0	0
T148	1989	7	0	0
T149	73079	245	0	0
T150	9513	43	0	0
T151	2171	4	0	0
T152	7376	8	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2055	0	0
T89	6825	28	0	0
T116	12390	40	0	0
T146	4652	6	0	0
T147	52692	423	0	0
T148	1989	1	0	0
T149	73079	219	0	0
T150	9513	8	0	0
T151	2171	4	0	0
T152	7376	7	0	0
T155	5601	6	0	0