Module Definition
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Module : kmac_errchk
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.93 96.83 96.67 80.00 96.15 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_errchk.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_errchk 93.93 96.83 96.67 80.00 96.15 100.00



Module Instance : tb.dut.u_errchk

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.93 96.83 96.67 80.00 96.15 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.04 97.22 96.67 80.00 96.30 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.24 96.27 93.33 100.00 100.00 93.85 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_regs 100.00 100.00 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : kmac_errchk
Line No.TotalCoveredPercent
TOTAL636196.83
ALWAYS187151386.67
CONT_ASSIGN23611100.00
ALWAYS24444100.00
ALWAYS25044100.00
ALWAYS26644100.00
CONT_ASSIGN30400
ALWAYS30966100.00
ALWAYS32255100.00
CONT_ASSIGN37611100.00
ALWAYS39133100.00
CONT_ASSIGN39911100.00
ALWAYS4021919100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_errchk.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_errchk.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
187 1 1
188 1 1
190 1 1
193 1 1
194 1 1
MISSING_ELSE
200 1 1
201 1 1
MISSING_ELSE
206 1 1
207 0 1
MISSING_ELSE
213 1 1
214 1 1
MISSING_ELSE
219 1 1
220 0 1
MISSING_ELSE
225 1 1
226 1 1
236 1 1
244 2 2
245 2 2
MISSING_ELSE
250 1 1
252 1 1
254 1 1
258 1 1
MISSING_ELSE
MISSING_ELSE
266 1 1
268 1 1
269 1 1
270 1 1
MISSING_ELSE
MISSING_ELSE
304 unreachable
309 1 1
310 1 1
311 1 1
312 1 1
313 1 1
314 1 1
322 1 1
324 1 1
326 1 1
337 1 1
349 1 1
359 unreachable
376 1 1
391 3 3
399 1 1
402 1 1
404 1 1
406 1 1
409 1 1
MISSING_ELSE
414 1 1
415 1 1
MISSING_ELSE
420 1 1
421 1 1
MISSING_ELSE
426 1 1
427 1 1
428 1 1
429 1 1
MISSING_ELSE
434 1 1
435 1 1
MISSING_ELSE
441 1 1
453 1 1
454 1 1
MISSING_ELSE
457 1 1
459 1 1
MISSING_ELSE


Cond Coverage for Module : kmac_errchk
TotalCoveredPercent
Conditions605896.67
Logical605896.67
Non-Logical00
Event00

 LINE       206
 EXPRESSION (sw_cmd_i != CmdNone)
            ----------1----------
-1-StatusTests
0CoveredT1,T3,T4
1Not Covered

 LINE       219
 EXPRESSION (sw_cmd_i != CmdNone)
            ----------1----------
-1-StatusTests
0CoveredT4,T15,T16
1Not Covered

 LINE       236
 EXPRESSION (err_swsequence || (err_modestrength && ((!cfg_en_unsupported_modestrength_i))) || err_entropy_ready)
             -------1------    ------------------------------2-----------------------------    --------3--------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001Unreachable
010CoveredT27,T28,T29
100CoveredT27,T28,T29

 LINE       236
 SUB-EXPRESSION (err_modestrength && ((!cfg_en_unsupported_modestrength_i)))
                 --------1-------    -------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT27,T28,T29
11CoveredT27,T28,T29

 LINE       252
 EXPRESSION ((st == StIdle) && (st_d == StMsgFeed))
             -------1------    ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       252
 SUB-EXPRESSION (st == StIdle)
                -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       252
 SUB-EXPRESSION (st_d == StMsgFeed)
                ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       254
 EXPRESSION 
 Number  Term
      1  (((cfg_mode_i == Sha3) && (cfg_strength_i inside {L224, L256, L384, L512})) || (((cfg_mode_i == Shake) || (cfg_mode_i == CShake)) && (cfg_strength_i inside {L128, L256}))) )
-1-StatusTests
0CoveredT27,T28,T29
1CoveredT1,T2,T3

 LINE       254
 SUB-EXPRESSION 
 Number  Term
      1  ((cfg_mode_i == Sha3) && (cfg_strength_i inside {L224, L256, L384, L512})) || 
      2  (((cfg_mode_i == Shake) || (cfg_mode_i == CShake)) && (cfg_strength_i inside {L128, L256})))
-1--2-StatusTests
00CoveredT27,T28,T29
01CoveredT2,T3,T4
10CoveredT1,T4,T14

 LINE       254
 SUB-EXPRESSION ((cfg_mode_i == Sha3) && (cfg_strength_i inside {L224, L256, L384, L512}))
                 ----------1---------    ------------------------2-----------------------
-1--2-StatusTests
01CoveredT2,T4,T15
10CoveredT27,T28,T29
11CoveredT1,T4,T14

 LINE       254
 SUB-EXPRESSION (cfg_mode_i == Sha3)
                ----------1---------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT1,T4,T14

 LINE       254
 SUB-EXPRESSION (((cfg_mode_i == Shake) || (cfg_mode_i == CShake)) && (cfg_strength_i inside {L128, L256}))
                 ------------------------1------------------------    ------------------2-----------------
-1--2-StatusTests
01CoveredT51,T22,T23
10CoveredT27,T28,T29
11CoveredT2,T3,T4

 LINE       254
 SUB-EXPRESSION ((cfg_mode_i == Shake) || (cfg_mode_i == CShake))
                 ----------1----------    -----------2----------
-1--2-StatusTests
00CoveredT1,T4,T14
01CoveredT4,T15,T16
10CoveredT2,T3,T4

 LINE       254
 SUB-EXPRESSION (cfg_mode_i == Shake)
                ----------1----------
-1-StatusTests
0CoveredT1,T4,T14
1CoveredT2,T3,T4

 LINE       254
 SUB-EXPRESSION (cfg_mode_i == CShake)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T15,T16

 LINE       268
 EXPRESSION ((st == StIdle) && (st_d == StMsgFeed) && kmac_en_i)
             -------1------    ---------2---------    ----3----
-1--2--3-StatusTests
011CoveredT4,T15,T16
101CoveredT4,T13,T15
110CoveredT1,T2,T3
111CoveredT4,T15,T16

 LINE       268
 SUB-EXPRESSION (st == StIdle)
                -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       268
 SUB-EXPRESSION (st_d == StMsgFeed)
                ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       269
 EXPRESSION (cfg_prefix_6B_i != kmac_pkg::EncodedStringKMAC)
            ------------------------1-----------------------
-1-StatusTests
0CoveredT4,T15,T16
1CoveredT27,T28,T29

 LINE       399
 EXPRESSION (block_swcmd ? st : st_d)
             -----1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT27,T28,T29

 LINE       406
 EXPRESSION (((!app_active_i)) && (sw_cmd_i == CmdStart))
             --------1--------    -----------2----------
-1--2-StatusTests
01CoveredT27,T29,T30
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       406
 SUB-EXPRESSION (sw_cmd_i == CmdStart)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       414
 EXPRESSION (sw_cmd_i == CmdProcess)
            ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       426
 EXPRESSION (sw_cmd_i == CmdManualRun)
            -------------1------------
-1-StatusTests
0CoveredT1,T3,T4
1CoveredT4,T15,T16

 LINE       428
 EXPRESSION (sw_cmd_i == CmdDone)
            ----------1----------
-1-StatusTests
0CoveredT1,T3,T4
1CoveredT1,T3,T4

FSM Coverage for Module : kmac_errchk
Summary for FSM :: st
TotalCoveredPercent
States 6 6 100.00 (Not included in score)
Transitions 15 12 80.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: st
statesLine No.CoveredTests
StAbsorbed 421 Covered T1,T3,T4
StIdle 429 Covered T1,T2,T3
StMsgFeed 409 Covered T1,T2,T3
StProcessing 415 Covered T1,T3,T4
StSqueezing 427 Covered T4,T15,T16
StTerminalError 454 Covered T2,T5,T6


transitionsLine No.CoveredTests
StAbsorbed->StIdle 429 Covered T1,T3,T4
StAbsorbed->StSqueezing 427 Covered T4,T15,T16
StAbsorbed->StTerminalError 454 Covered T54,T55,T56
StIdle->StMsgFeed 409 Covered T1,T2,T3
StIdle->StTerminalError 454 Covered T5,T34,T35
StMsgFeed->StIdle 459 Not Covered
StMsgFeed->StProcessing 415 Covered T1,T3,T4
StMsgFeed->StTerminalError 454 Covered T2,T6,T37
StProcessing->StAbsorbed 421 Covered T1,T3,T4
StProcessing->StIdle 459 Covered T85,T86
StProcessing->StTerminalError 454 Covered T87
StSqueezing->StAbsorbed 435 Covered T4,T15,T16
StSqueezing->StIdle 459 Not Covered
StSqueezing->StTerminalError 454 Not Covered
StTerminalError->StIdle 459 Covered T2,T5,T6



Branch Coverage for Module : kmac_errchk
Line No.TotalCoveredPercent
Branches 52 50 96.15
TERNARY 399 2 2 100.00
CASE 190 12 10 83.33
IF 244 3 3 100.00
IF 252 3 3 100.00
IF 268 3 3 100.00
CASE 309 6 6 100.00
CASE 324 4 4 100.00
IF 391 2 2 100.00
CASE 404 13 13 100.00
IF 453 2 2 100.00
IF 457 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_errchk.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_errchk.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 399 (block_swcmd) ?

Branches:
-1-StatusTests
1 Covered T27,T28,T29
0 Covered T1,T2,T3


LineNo. Expression -1-: 190 case (st) -2-: 193 if ((!(sw_cmd_i inside {CmdNone, CmdStart}))) -3-: 200 if ((!(sw_cmd_i inside {CmdNone, CmdProcess}))) -4-: 206 if ((sw_cmd_i != CmdNone)) -5-: 213 if ((!(sw_cmd_i inside {CmdNone, CmdManualRun, CmdDone}))) -6-: 219 if ((sw_cmd_i != CmdNone))

Branches:
-1--2--3--4--5--6-StatusTests
StIdle 1 - - - - Covered T27,T28,T29
StIdle 0 - - - - Covered T1,T2,T3
StMsgFeed - 1 - - - Covered T27,T28,T29
StMsgFeed - 0 - - - Covered T1,T2,T3
StProcessing - - 1 - - Not Covered
StProcessing - - 0 - - Covered T1,T3,T4
StAbsorbed - - - 1 - Covered T27,T28,T29
StAbsorbed - - - 0 - Covered T1,T3,T4
StSqueezing - - - - 1 Not Covered
StSqueezing - - - - 0 Covered T4,T15,T16
StTerminalError - - - - - Covered T2,T5,T6
default - - - - - Covered T10,T11,T12


LineNo. Expression -1-: 244 if ((!rst_ni)) -2-: 245 if ((!block_swcmd))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T27,T28,T29


LineNo. Expression -1-: 252 if (((st == StIdle) && (st_d == StMsgFeed))) -2-: 254 if ((!(((cfg_mode_i == Sha3) && (cfg_strength_i inside {L224, L256, L384, L512})) || (((cfg_mode_i == Shake) || (cfg_mode_i == CShake)) && (cfg_strength_i inside {L128, L256})))))

Branches:
-1--2-StatusTests
1 1 Covered T27,T28,T29
1 0 Covered T1,T2,T3
0 - Covered T1,T2,T3


LineNo. Expression -1-: 268 if ((((st == StIdle) && (st_d == StMsgFeed)) && kmac_en_i)) -2-: 269 if ((cfg_prefix_6B_i != kmac_pkg::EncodedStringKMAC))

Branches:
-1--2-StatusTests
1 1 Covered T27,T28,T29
1 0 Covered T4,T15,T16
0 - Covered T1,T2,T3


LineNo. Expression -1-: 309 case (st)

Branches:
-1-StatusTests
StIdle Covered T1,T2,T3
StMsgFeed Covered T1,T2,T3
StProcessing Covered T1,T3,T4
StAbsorbed Covered T1,T3,T4
StSqueezing Covered T4,T15,T16
default Covered T2,T5,T6


LineNo. Expression -1-: 324 case (1'b1)

Branches:
-1-StatusTests
err_swsequence Covered T27,T28,T29
err_modestrength Covered T27,T28,T29
err_prefix Covered T27,T28,T29
err_entropy_ready Unreachable
default Covered T1,T2,T3


LineNo. Expression -1-: 391 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 404 case (st) -2-: 406 if (((!app_active_i) && (sw_cmd_i == CmdStart))) -3-: 414 if ((sw_cmd_i == CmdProcess)) -4-: 420 if (prim_mubi_pkg::mubi4_test_true_strict(sha3_absorbed_i)) -5-: 426 if ((sw_cmd_i == CmdManualRun)) -6-: 428 if ((sw_cmd_i == CmdDone)) -7-: 434 if (keccak_done_i)

Branches:
-1--2--3--4--5--6--7-StatusTests
StIdle 1 - - - - - Covered T1,T2,T3
StIdle 0 - - - - - Covered T1,T2,T3
StMsgFeed - 1 - - - - Covered T1,T3,T4
StMsgFeed - 0 - - - - Covered T1,T2,T3
StProcessing - - 1 - - - Covered T1,T3,T4
StProcessing - - 0 - - - Covered T1,T3,T4
StAbsorbed - - - 1 - - Covered T4,T15,T16
StAbsorbed - - - 0 1 - Covered T1,T3,T4
StAbsorbed - - - 0 0 - Covered T1,T3,T4
StSqueezing - - - - - 1 Covered T4,T15,T16
StSqueezing - - - - - 0 Covered T4,T15,T16
StTerminalError - - - - - - Covered T2,T5,T6
default - - - - - - Covered T10,T11,T12


LineNo. Expression -1-: 453 if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i))

Branches:
-1-StatusTests
1 Covered T2,T5,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 457 if (((st_d != StTerminalError) && prim_mubi_pkg::mubi4_test_true_strict(clear_after_error_i)))

Branches:
-1-StatusTests
1 Covered T13,T17,T20
0 Covered T1,T2,T3


Assert Coverage for Module : kmac_errchk
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
ExpectedModeStrengthBits_A 1032 1032 0 0
ExpectedStSwCmdBits_A 1032 1032 0 0
StKnown_A 2147483647 2147483647 0 0
u_state_regs_A 2147483647 2147483647 0 0


ExpectedModeStrengthBits_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1032 1032 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

ExpectedStSwCmdBits_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1032 1032 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

StKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 945066 944977 0 0
T2 3922 3779 0 0
T3 514200 514193 0 0
T4 203288 203236 0 0
T13 83880 83821 0 0
T14 965561 965499 0 0
T15 154500 154494 0 0
T16 191476 191467 0 0
T17 101559 101493 0 0
T18 265303 265296 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 945066 944977 0 0
T2 3922 3779 0 0
T3 514200 514193 0 0
T4 203288 203236 0 0
T13 83880 83821 0 0
T14 965561 965499 0 0
T15 154500 154494 0 0
T16 191476 191467 0 0
T17 101559 101493 0 0
T18 265303 265296 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%