Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	260528653	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

205495491

1

T1

107673

T2

719

T3

620

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	245997471	1			T1	121175		T2	166		T3	349
values[0x0]	105666852	1			T1	24918		T2	366		T3	333
values[0x1]	114359821	1			T1	26648		T2	372		T3	299

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	203021830	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

263002314

1

T1

122767

T2

765

T3

720

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1450997	1			T1	709		T2	2		T3	3
valid_sources[0x01]	3376959	1			T1	715		T3	3		T13	9339
valid_sources[0x02]	1455442	1			T1	685		T3	3		T13	8365
valid_sources[0x03]	2375819	1			T1	677		T2	10		T3	5
valid_sources[0x04]	1448478	1			T1	662		T3	4		T13	8742
valid_sources[0x05]	1917457	1			T1	650		T2	3		T3	5
valid_sources[0x06]	2390860	1			T1	676		T2	8		T3	4
valid_sources[0x07]	1454372	1			T1	677		T3	2		T13	9094
valid_sources[0x08]	1906103	1			T1	606		T2	5		T3	2
valid_sources[0x09]	1447407	1			T1	661		T2	1		T3	5
valid_sources[0x0a]	4110301	1			T1	635		T3	2		T13	9239
valid_sources[0x0b]	1448146	1			T1	664		T3	3		T13	9629
valid_sources[0x0c]	1459175	1			T1	650		T13	9345		T14	25
valid_sources[0x0d]	1449684	1			T1	689		T2	5		T3	3
valid_sources[0x0e]	1449955	1			T1	664		T2	7		T3	7
valid_sources[0x0f]	1449786	1			T1	654		T2	5		T3	5
valid_sources[0x10]	2327141	1			T1	720		T2	3		T3	6
valid_sources[0x11]	1457109	1			T1	693		T2	11		T3	3
valid_sources[0x12]	1461593	1			T1	678		T2	6		T3	2
valid_sources[0x13]	1453302	1			T1	660		T2	3		T3	2
valid_sources[0x14]	1454774	1			T1	640		T2	3		T3	2
valid_sources[0x15]	1451264	1			T1	693		T3	10		T13	10032
valid_sources[0x16]	1447469	1			T1	686		T2	2		T3	2
valid_sources[0x17]	2570655	1			T1	635		T2	2		T3	3
valid_sources[0x18]	1471680	1			T1	673		T2	9		T3	3
valid_sources[0x19]	1448909	1			T1	717		T2	10		T3	1
valid_sources[0x1a]	2312572	1			T1	659		T3	1		T13	9014
valid_sources[0x1b]	3865246	1			T1	647		T2	2		T3	4
valid_sources[0x1c]	1463885	1			T1	601		T2	5		T3	2
valid_sources[0x1d]	3501035	1			T1	685		T2	6		T3	5
valid_sources[0x1e]	1451449	1			T1	661		T2	4		T3	2
valid_sources[0x1f]	1555556	1			T1	652		T2	5		T3	3
valid_sources[0x20]	2336792	1			T1	701		T3	5		T13	9136
valid_sources[0x21]	1452562	1			T1	691		T2	8		T3	6
valid_sources[0x22]	1457100	1			T1	713		T2	5		T3	3
valid_sources[0x23]	2387273	1			T1	677		T2	2		T3	1
valid_sources[0x24]	5521821	1			T1	729		T2	3		T3	2
valid_sources[0x25]	3902786	1			T1	664		T3	2		T13	10381
valid_sources[0x26]	2314341	1			T1	680		T2	5		T3	3
valid_sources[0x27]	2393479	1			T1	662		T2	1		T3	6
valid_sources[0x28]	1455145	1			T1	683		T2	3		T3	3
valid_sources[0x29]	1453027	1			T1	678		T2	9		T3	1
valid_sources[0x2a]	1445296	1			T1	651		T3	6		T13	9421
valid_sources[0x2b]	1452058	1			T1	705		T2	1		T13	9179
valid_sources[0x2c]	1501987	1			T1	708		T2	2		T3	4
valid_sources[0x2d]	1453000	1			T1	688		T2	3		T3	4
valid_sources[0x2e]	1442256	1			T1	689		T2	9		T3	3
valid_sources[0x2f]	1556144	1			T1	645		T2	6		T3	4
valid_sources[0x30]	1447911	1			T1	671		T3	1		T13	9674
valid_sources[0x31]	1453698	1			T1	673		T3	6		T13	9328
valid_sources[0x32]	4944344	1			T1	698		T2	6		T3	4
valid_sources[0x33]	1728051	1			T1	725		T2	5		T3	5
valid_sources[0x34]	1485719	1			T1	655		T2	1		T3	1
valid_sources[0x35]	2965511	1			T1	695		T3	7		T13	9570
valid_sources[0x36]	3885590	1			T1	649		T2	5		T3	2
valid_sources[0x37]	1512590	1			T1	681		T2	3		T3	11
valid_sources[0x38]	1471660	1			T1	656		T3	4		T13	9354
valid_sources[0x39]	1437031	1			T1	664		T2	5		T3	8
valid_sources[0x3a]	1441724	1			T1	690		T3	1		T13	9454
valid_sources[0x3b]	1466404	1			T1	665		T2	5		T3	4
valid_sources[0x3c]	1446313	1			T1	670		T2	3		T3	4
valid_sources[0x3d]	1498636	1			T1	659		T2	1		T3	4
valid_sources[0x3e]	1457630	1			T1	645		T2	2		T3	6
valid_sources[0x3f]	1574484	1			T1	688		T2	2		T13	8768
valid_sources[0x40]	1921102	1			T1	725		T2	1		T3	4
valid_sources[0x41]	1451424	1			T1	672		T2	8		T3	2
valid_sources[0x42]	1451793	1			T1	695		T2	1		T3	3
valid_sources[0x43]	4079368	1			T1	729		T3	6		T13	8640
valid_sources[0x44]	1446546	1			T1	650		T2	11		T3	3
valid_sources[0x45]	2103107	1			T1	633		T2	3		T3	8
valid_sources[0x46]	2711017	1			T1	711		T2	3		T3	9
valid_sources[0x47]	1515079	1			T1	692		T3	6		T13	9388
valid_sources[0x48]	1456300	1			T1	652		T2	1		T3	2
valid_sources[0x49]	1450484	1			T1	664		T2	3		T3	9
valid_sources[0x4a]	1447393	1			T1	663		T2	9		T3	11
valid_sources[0x4b]	1482343	1			T1	630		T2	6		T3	1
valid_sources[0x4c]	1456740	1			T1	696		T2	4		T3	1
valid_sources[0x4d]	1634058	1			T1	685		T2	2		T3	3
valid_sources[0x4e]	1446011	1			T1	753		T2	3		T3	2
valid_sources[0x4f]	1462907	1			T1	675		T3	5		T13	9806
valid_sources[0x50]	1452854	1			T1	687		T2	2		T3	6
valid_sources[0x51]	1456802	1			T1	667		T2	4		T3	4
valid_sources[0x52]	3584289	1			T1	709		T2	7		T13	9002
valid_sources[0x53]	1439986	1			T1	656		T2	4		T13	9447
valid_sources[0x54]	2372653	1			T1	661		T2	8		T3	5
valid_sources[0x55]	1636482	1			T1	691		T2	1		T3	2
valid_sources[0x56]	1605246	1			T1	667		T2	2		T3	4
valid_sources[0x57]	1459019	1			T1	669		T2	8		T3	5
valid_sources[0x58]	1450366	1			T1	692		T2	2		T3	4
valid_sources[0x59]	1444913	1			T1	652		T2	7		T3	5
valid_sources[0x5a]	1455890	1			T1	633		T2	7		T3	2
valid_sources[0x5b]	1497732	1			T1	716		T2	1		T3	3
valid_sources[0x5c]	1449574	1			T1	660		T2	6		T3	9
valid_sources[0x5d]	2127900	1			T1	641		T2	7		T3	5
valid_sources[0x5e]	1946638	1			T1	653		T2	2		T3	6
valid_sources[0x5f]	1447331	1			T1	710		T2	2		T3	4
valid_sources[0x60]	1447887	1			T1	649		T2	1		T3	4
valid_sources[0x61]	1457454	1			T1	628		T2	4		T3	4
valid_sources[0x62]	1455110	1			T1	717		T2	1		T13	10379
valid_sources[0x63]	1455060	1			T1	662		T2	3		T3	8
valid_sources[0x64]	1457242	1			T1	607		T2	7		T3	3
valid_sources[0x65]	1444441	1			T1	644		T2	2		T3	3
valid_sources[0x66]	1570697	1			T1	719		T2	1		T3	4
valid_sources[0x67]	1441873	1			T1	674		T2	4		T3	6
valid_sources[0x68]	1455349	1			T1	686		T3	7		T13	9446
valid_sources[0x69]	1447474	1			T1	687		T3	2		T13	9280
valid_sources[0x6a]	1451286	1			T1	694		T2	3		T3	5
valid_sources[0x6b]	2012110	1			T1	596		T2	5		T3	4
valid_sources[0x6c]	1496715	1			T1	728		T2	11		T3	7
valid_sources[0x6d]	2127717	1			T1	681		T2	9		T3	11
valid_sources[0x6e]	1457544	1			T1	654		T2	8		T3	5
valid_sources[0x6f]	1447567	1			T1	702		T3	10		T13	9323
valid_sources[0x70]	1599977	1			T1	699		T3	5		T13	9295
valid_sources[0x71]	1445650	1			T1	705		T2	6		T3	2
valid_sources[0x72]	1459748	1			T1	624		T2	6		T3	1
valid_sources[0x73]	3856127	1			T1	675		T3	2		T13	8723
valid_sources[0x74]	1465387	1			T1	645		T2	10		T3	1
valid_sources[0x75]	1453197	1			T1	606		T2	22		T3	7
valid_sources[0x76]	1454033	1			T1	663		T2	6		T3	7
valid_sources[0x77]	1446921	1			T1	678		T2	2		T3	5
valid_sources[0x78]	1564314	1			T1	642		T2	6		T3	1
valid_sources[0x79]	1479981	1			T1	655		T2	9		T3	2
valid_sources[0x7a]	1457034	1			T1	705		T2	3		T3	2
valid_sources[0x7b]	1457830	1			T1	651		T2	3		T3	1
valid_sources[0x7c]	1442581	1			T1	625		T2	4		T3	2
valid_sources[0x7d]	3815337	1			T1	679		T2	3		T3	5
valid_sources[0x7e]	1452262	1			T1	691		T2	3		T3	3
valid_sources[0x7f]	1457803	1			T1	684		T2	3		T3	1
valid_sources[0x80]	1462484	1			T1	733		T2	2		T13	9371

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

89868589

1

T1

80026

T2

23

T3

22

values[0x0]

all_enables

biggest_size

62198676

1

T1

14867

T2

339

T3

313

values[0x1]

all_enables

biggest_size

53428226

1

T1

12780

T2

357

T3

285