Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

262758177

1

T1

65068

T2

185

T3

361

full_word

205636026

1

T1

107673

T2

719

T3

620

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	468393873	1			T1	172741		T2	904		T3	981
auto[TlIntgErrCmd]	106	1			T110	4		T111	4		T112	6
auto[TlIntgErrData]	102	1			T110	4		T111	2		T112	9
auto[TlIntgErrBoth]	122	1			T110	2		T111	4		T112	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

246430892

1

T1

121175

T2

166

T3

349

auto[1]

221963311

1

T1

51566

T2

738

T3

632

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	156527107	1			T1	41149		T2	143		T3	327
auto[TlIntgErrNone]	partial	auto[1]	106230762	1			T1	23919		T2	42		T3	34
auto[TlIntgErrNone]	full_word	auto[0]	89903646	1			T1	80026		T2	23		T3	22
auto[TlIntgErrNone]	full_word	auto[1]	115732358	1			T1	27647		T2	696		T3	598
auto[TlIntgErrCmd]	partial	auto[0]	38	1			T110	1		T111	1		T112	1
auto[TlIntgErrCmd]	partial	auto[1]	61	1			T110	3		T111	1		T112	4
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T111	1		T112	1		T167	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T111	1		T136	2		T168	1
auto[TlIntgErrData]	partial	auto[0]	48	1			T110	3		T111	1		T112	5
auto[TlIntgErrData]	partial	auto[1]	47	1			T110	1		T111	1		T112	4
auto[TlIntgErrData]	full_word	auto[0]	3	1			T136	1		T169	1		T170	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T136	1		T171	1		T172	1
auto[TlIntgErrBoth]	partial	auto[0]	44	1			T110	1		T111	1		T112	2
auto[TlIntgErrBoth]	partial	auto[1]	70	1			T110	1		T111	3		T112	3
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T173	1		T169	1		T172	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T173	2		T171	1		T167	1