Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	519382	0	0
entropy_period_rd_A	2147483647	2494	0	0
intr_enable_rd_A	2147483647	3245	0	0
prefix_0_rd_A	2147483647	2625	0	0
prefix_10_rd_A	2147483647	2681	0	0
prefix_1_rd_A	2147483647	2537	0	0
prefix_2_rd_A	2147483647	2601	0	0
prefix_3_rd_A	2147483647	2541	0	0
prefix_4_rd_A	2147483647	2703	0	0
prefix_5_rd_A	2147483647	2707	0	0
prefix_6_rd_A	2147483647	2411	0	0
prefix_7_rd_A	2147483647	2718	0	0
prefix_8_rd_A	2147483647	2708	0	0
prefix_9_rd_A	2147483647	2550	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	519382	0	0
T4	2188	0	0	0
T17	233995	22547	0	0
T18	458740	0	0	0
T19	111566	0	0	0
T24	360798	0	0	0
T25	345356	0	0	0
T37	766251	0	0	0
T43	0	53260	0	0
T52	0	13853	0	0
T77	0	48742	0	0
T84	187324	0	0	0
T86	0	20726	0	0
T87	0	119970	0	0
T88	0	74220	0	0
T93	216955	0	0	0
T94	0	22043	0	0
T117	0	27934	0	0
T118	0	58028	0	0
T119	174512	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2494	0	0
T94	262934	59	0	0
T100	0	6	0	0
T102	0	26	0	0
T104	0	28	0	0
T111	0	78	0	0
T132	0	236	0	0
T133	0	78	0	0
T134	0	1	0	0
T135	0	23	0	0
T136	0	135	0	0
T137	254910	0	0	0
T138	218821	0	0	0
T139	398567	0	0	0
T140	433061	0	0	0
T141	139152	0	0	0
T142	159116	0	0	0
T143	222061	0	0	0
T144	356482	0	0	0
T145	125403	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3245	0	0
T94	262934	60	0	0
T100	0	7	0	0
T102	0	21	0	0
T104	0	30	0	0
T111	0	70	0	0
T132	0	432	0	0
T133	0	204	0	0
T134	0	14	0	0
T137	254910	0	0	0
T138	218821	0	0	0
T139	398567	0	0	0
T140	433061	0	0	0
T141	139152	0	0	0
T142	159116	0	0	0
T143	222061	0	0	0
T144	356482	0	0	0
T145	125403	0	0	0
T146	0	19	0	0
T147	0	16	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2625	0	0
T94	262934	47	0	0
T100	0	7	0	0
T102	0	18	0	0
T104	0	19	0	0
T111	0	14	0	0
T132	0	453	0	0
T133	0	211	0	0
T134	0	6	0	0
T135	0	26	0	0
T137	254910	0	0	0
T138	218821	0	0	0
T139	398567	0	0	0
T140	433061	0	0	0
T141	139152	0	0	0
T142	159116	0	0	0
T143	222061	0	0	0
T144	356482	0	0	0
T145	125403	0	0	0
T148	0	7	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2681	0	0
T94	262934	97	0	0
T100	0	9	0	0
T102	0	19	0	0
T103	0	5	0	0
T104	0	12	0	0
T111	0	38	0	0
T132	0	450	0	0
T133	0	217	0	0
T134	0	7	0	0
T136	0	100	0	0
T137	254910	0	0	0
T138	218821	0	0	0
T139	398567	0	0	0
T140	433061	0	0	0
T141	139152	0	0	0
T142	159116	0	0	0
T143	222061	0	0	0
T144	356482	0	0	0
T145	125403	0	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2537	0	0
T94	262934	72	0	0
T102	0	25	0	0
T103	0	5	0	0
T104	0	23	0	0
T111	0	30	0	0
T132	0	404	0	0
T133	0	257	0	0
T134	0	3	0	0
T135	0	11	0	0
T137	254910	0	0	0
T138	218821	0	0	0
T139	398567	0	0	0
T140	433061	0	0	0
T141	139152	0	0	0
T142	159116	0	0	0
T143	222061	0	0	0
T144	356482	0	0	0
T145	125403	0	0	0
T148	0	6	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2601	0	0
T94	262934	67	0	0
T100	0	15	0	0
T102	0	27	0	0
T103	0	1	0	0
T104	0	18	0	0
T111	0	40	0	0
T132	0	402	0	0
T133	0	248	0	0
T134	0	2	0	0
T137	254910	0	0	0
T138	218821	0	0	0
T139	398567	0	0	0
T140	433061	0	0	0
T141	139152	0	0	0
T142	159116	0	0	0
T143	222061	0	0	0
T144	356482	0	0	0
T145	125403	0	0	0
T148	0	6	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2541	0	0
T94	262934	64	0	0
T100	0	9	0	0
T102	0	10	0	0
T103	0	4	0	0
T104	0	30	0	0
T111	0	47	0	0
T132	0	431	0	0
T133	0	232	0	0
T134	0	7	0	0
T135	0	3	0	0
T137	254910	0	0	0
T138	218821	0	0	0
T139	398567	0	0	0
T140	433061	0	0	0
T141	139152	0	0	0
T142	159116	0	0	0
T143	222061	0	0	0
T144	356482	0	0	0
T145	125403	0	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2703	0	0
T94	262934	87	0	0
T100	0	11	0	0
T102	0	23	0	0
T104	0	23	0	0
T111	0	26	0	0
T132	0	528	0	0
T133	0	249	0	0
T134	0	4	0	0
T135	0	2	0	0
T137	254910	0	0	0
T138	218821	0	0	0
T139	398567	0	0	0
T140	433061	0	0	0
T141	139152	0	0	0
T142	159116	0	0	0
T143	222061	0	0	0
T144	356482	0	0	0
T145	125403	0	0	0
T148	0	1	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2707	0	0
T94	262934	95	0	0
T100	0	12	0	0
T102	0	19	0	0
T103	0	1	0	0
T104	0	27	0	0
T111	0	29	0	0
T132	0	467	0	0
T133	0	248	0	0
T134	0	1	0	0
T137	254910	0	0	0
T138	218821	0	0	0
T139	398567	0	0	0
T140	433061	0	0	0
T141	139152	0	0	0
T142	159116	0	0	0
T143	222061	0	0	0
T144	356482	0	0	0
T145	125403	0	0	0
T148	0	2	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2411	0	0
T94	262934	56	0	0
T100	0	17	0	0
T102	0	24	0	0
T103	0	6	0	0
T104	0	28	0	0
T111	0	35	0	0
T132	0	463	0	0
T133	0	244	0	0
T134	0	4	0	0
T137	254910	0	0	0
T138	218821	0	0	0
T139	398567	0	0	0
T140	433061	0	0	0
T141	139152	0	0	0
T142	159116	0	0	0
T143	222061	0	0	0
T144	356482	0	0	0
T145	125403	0	0	0
T148	0	3	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2718	0	0
T94	262934	67	0	0
T100	0	13	0	0
T102	0	17	0	0
T104	0	34	0	0
T111	0	38	0	0
T132	0	506	0	0
T133	0	244	0	0
T134	0	1	0	0
T135	0	27	0	0
T137	254910	0	0	0
T138	218821	0	0	0
T139	398567	0	0	0
T140	433061	0	0	0
T141	139152	0	0	0
T142	159116	0	0	0
T143	222061	0	0	0
T144	356482	0	0	0
T145	125403	0	0	0
T148	0	7	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2708	0	0
T94	262934	69	0	0
T100	0	11	0	0
T102	0	15	0	0
T104	0	27	0	0
T111	0	46	0	0
T132	0	450	0	0
T133	0	223	0	0
T134	0	2	0	0
T137	254910	0	0	0
T138	218821	0	0	0
T139	398567	0	0	0
T140	433061	0	0	0
T141	139152	0	0	0
T142	159116	0	0	0
T143	222061	0	0	0
T144	356482	0	0	0
T145	125403	0	0	0
T148	0	5	0	0
T149	0	7	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2550	0	0
T94	262934	59	0	0
T102	0	14	0	0
T104	0	14	0	0
T111	0	41	0	0
T132	0	426	0	0
T133	0	221	0	0
T134	0	2	0	0
T135	0	34	0	0
T136	0	67	0	0
T137	254910	0	0	0
T138	218821	0	0	0
T139	398567	0	0	0
T140	433061	0	0	0
T141	139152	0	0	0
T142	159116	0	0	0
T143	222061	0	0	0
T144	356482	0	0	0
T145	125403	0	0	0
T148	0	7	0	0