Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

257873616

1

T1

1967

T2

798

T3

6850

full_word

202492418

1

T1

4816

T2

1399

T3

91693

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	460365754	1			T1	6783		T2	2197		T3	98543
auto[TlIntgErrCmd]	101	1			T107	6		T108	7		T109	1
auto[TlIntgErrData]	92	1			T107	2		T108	7		T109	6
auto[TlIntgErrBoth]	87	1			T107	2		T108	6		T109	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

240667477

1

T1

4909

T2

1143

T3

27580

auto[1]

219698557

1

T1

1874

T2

1054

T3

70963

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	153005979	1			T1	1255		T2	447		T3	5760
auto[TlIntgErrNone]	partial	auto[1]	104867376	1			T1	712		T2	351		T3	1090
auto[TlIntgErrNone]	full_word	auto[0]	87661385	1			T1	3654		T2	696		T3	21820
auto[TlIntgErrNone]	full_word	auto[1]	114831014	1			T1	1162		T2	703		T3	69873
auto[TlIntgErrCmd]	partial	auto[0]	37	1			T108	2		T163	2		T164	1
auto[TlIntgErrCmd]	partial	auto[1]	57	1			T107	4		T108	5		T109	1
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T107	2		T170	1		T171	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T165	1		T172	1		T173	1
auto[TlIntgErrData]	partial	auto[0]	33	1			T107	2		T108	1		T109	3
auto[TlIntgErrData]	partial	auto[1]	52	1			T108	6		T109	2		T163	4
auto[TlIntgErrData]	full_word	auto[0]	5	1			T109	1		T163	2		T168	1
auto[TlIntgErrData]	full_word	auto[1]	2	1			T174	1		T175	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	33	1			T107	1		T108	2		T109	1
auto[TlIntgErrBoth]	partial	auto[1]	49	1			T107	1		T108	4		T109	2
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T113	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T176	1		T175	1		T171	1