Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	891724	0	0
entropy_period_rd_A	2147483647	2020	0	0
intr_enable_rd_A	2147483647	2237	0	0
prefix_0_rd_A	2147483647	1797	0	0
prefix_10_rd_A	2147483647	1748	0	0
prefix_1_rd_A	2147483647	1994	0	0
prefix_2_rd_A	2147483647	1877	0	0
prefix_3_rd_A	2147483647	1848	0	0
prefix_4_rd_A	2147483647	1897	0	0
prefix_5_rd_A	2147483647	1992	0	0
prefix_6_rd_A	2147483647	1819	0	0
prefix_7_rd_A	2147483647	1763	0	0
prefix_8_rd_A	2147483647	1827	0	0
prefix_9_rd_A	2147483647	1953	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	891724	0	0
T24	0	94089	0	0
T26	378273	54588	0	0
T28	706721	0	0	0
T33	0	32462	0	0
T34	0	105146	0	0
T49	0	31498	0	0
T53	1534	0	0	0
T85	5390	0	0	0
T88	0	21442	0	0
T89	0	54570	0	0
T104	34482	0	0	0
T105	223725	0	0	0
T114	0	54620	0	0
T115	0	29324	0	0
T116	0	88033	0	0
T117	17169	0	0	0
T118	633412	0	0	0
T119	120986	0	0	0
T120	187942	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2020	0	0
T68	56689	0	0	0
T88	256125	39	0	0
T89	0	63	0	0
T90	0	102	0	0
T92	0	13	0	0
T97	0	28	0	0
T128	0	146	0	0
T129	0	45	0	0
T130	0	31	0	0
T131	0	7	0	0
T132	0	421	0	0
T133	507602	0	0	0
T134	17445	0	0	0
T135	16203	0	0	0
T136	5873	0	0	0
T137	16285	0	0	0
T138	499229	0	0	0
T139	29069	0	0	0
T140	182127	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2237	0	0
T68	56689	0	0	0
T88	256125	20	0	0
T89	0	60	0	0
T90	0	74	0	0
T92	0	19	0	0
T110	0	24	0	0
T111	0	21	0	0
T128	0	94	0	0
T129	0	19	0	0
T133	507602	0	0	0
T134	17445	0	0	0
T135	16203	0	0	0
T136	5873	0	0	0
T137	16285	0	0	0
T138	499229	0	0	0
T139	29069	0	0	0
T140	182127	0	0	0
T141	0	21	0	0
T142	0	11	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1797	0	0
T68	56689	0	0	0
T88	256125	20	0	0
T89	0	67	0	0
T90	0	60	0	0
T92	0	10	0	0
T97	0	26	0	0
T128	0	106	0	0
T129	0	42	0	0
T130	0	5	0	0
T132	0	458	0	0
T133	507602	0	0	0
T134	17445	0	0	0
T135	16203	0	0	0
T136	5873	0	0	0
T137	16285	0	0	0
T138	499229	0	0	0
T139	29069	0	0	0
T140	182127	0	0	0
T143	0	46	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1748	0	0
T68	56689	0	0	0
T88	256125	29	0	0
T89	0	57	0	0
T90	0	82	0	0
T92	0	25	0	0
T97	0	4	0	0
T128	0	66	0	0
T129	0	48	0	0
T130	0	37	0	0
T131	0	5	0	0
T133	507602	0	0	0
T134	17445	0	0	0
T135	16203	0	0	0
T136	5873	0	0	0
T137	16285	0	0	0
T138	499229	0	0	0
T139	29069	0	0	0
T140	182127	0	0	0
T144	0	2	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1994	0	0
T68	56689	0	0	0
T88	256125	35	0	0
T89	0	131	0	0
T90	0	61	0	0
T92	0	19	0	0
T97	0	26	0	0
T128	0	138	0	0
T129	0	47	0	0
T130	0	34	0	0
T131	0	5	0	0
T133	507602	0	0	0
T134	17445	0	0	0
T135	16203	0	0	0
T136	5873	0	0	0
T137	16285	0	0	0
T138	499229	0	0	0
T139	29069	0	0	0
T140	182127	0	0	0
T144	0	1	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1877	0	0
T68	56689	0	0	0
T88	256125	37	0	0
T89	0	63	0	0
T90	0	85	0	0
T92	0	17	0	0
T97	0	25	0	0
T128	0	123	0	0
T129	0	23	0	0
T130	0	39	0	0
T131	0	6	0	0
T132	0	437	0	0
T133	507602	0	0	0
T134	17445	0	0	0
T135	16203	0	0	0
T136	5873	0	0	0
T137	16285	0	0	0
T138	499229	0	0	0
T139	29069	0	0	0
T140	182127	0	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1848	0	0
T68	56689	0	0	0
T88	256125	40	0	0
T89	0	93	0	0
T90	0	98	0	0
T92	0	10	0	0
T97	0	20	0	0
T128	0	150	0	0
T129	0	47	0	0
T130	0	19	0	0
T131	0	7	0	0
T133	507602	0	0	0
T134	17445	0	0	0
T135	16203	0	0	0
T136	5873	0	0	0
T137	16285	0	0	0
T138	499229	0	0	0
T139	29069	0	0	0
T140	182127	0	0	0
T145	0	5	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1897	0	0
T68	56689	0	0	0
T88	256125	13	0	0
T89	0	60	0	0
T90	0	66	0	0
T92	0	20	0	0
T97	0	10	0	0
T128	0	165	0	0
T129	0	8	0	0
T130	0	7	0	0
T131	0	8	0	0
T132	0	487	0	0
T133	507602	0	0	0
T134	17445	0	0	0
T135	16203	0	0	0
T136	5873	0	0	0
T137	16285	0	0	0
T138	499229	0	0	0
T139	29069	0	0	0
T140	182127	0	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1992	0	0
T68	56689	0	0	0
T88	256125	38	0	0
T89	0	83	0	0
T90	0	67	0	0
T92	0	23	0	0
T97	0	30	0	0
T128	0	117	0	0
T129	0	69	0	0
T130	0	9	0	0
T131	0	9	0	0
T132	0	424	0	0
T133	507602	0	0	0
T134	17445	0	0	0
T135	16203	0	0	0
T136	5873	0	0	0
T137	16285	0	0	0
T138	499229	0	0	0
T139	29069	0	0	0
T140	182127	0	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1819	0	0
T68	56689	0	0	0
T88	256125	29	0	0
T89	0	99	0	0
T90	0	66	0	0
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T130	0	32	0	0
T131	0	2	0	0
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T138	499229	0	0	0
T139	29069	0	0	0
T140	182127	0	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1763	0	0
T68	56689	0	0	0
T88	256125	38	0	0
T89	0	69	0	0
T90	0	122	0	0
T92	0	17	0	0
T97	0	15	0	0
T128	0	114	0	0
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T130	0	18	0	0
T132	0	400	0	0
T133	507602	0	0	0
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T138	499229	0	0	0
T139	29069	0	0	0
T140	182127	0	0	0
T143	0	31	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1827	0	0
T68	56689	0	0	0
T88	256125	21	0	0
T89	0	84	0	0
T90	0	66	0	0
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prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1953	0	0
T68	56689	0	0	0
T88	256125	32	0	0
T89	0	89	0	0
T90	0	73	0	0
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