Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

255048452

1

T1

4286

T2

11

T3

25873

full_word

199371991

1

T1

23488

T2

147

T3

40915

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	454420143	1			T1	27774		T2	158		T3	66788
auto[TlIntgErrCmd]	92	1			T121	4		T122	2		T179	6
auto[TlIntgErrData]	102	1			T120	4		T121	7		T122	6
auto[TlIntgErrBoth]	106	1			T120	6		T121	9		T122	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

238522685

1

T1

18417

T2

74

T3

45823

auto[1]

215897758

1

T1

9357

T2

84

T3

20965

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	151939327	1			T1	2397		T2	4		T3	16438
auto[TlIntgErrNone]	partial	auto[1]	103108845	1			T1	1889		T2	7		T3	9435
auto[TlIntgErrNone]	full_word	auto[0]	86583228	1			T1	16020		T2	70		T3	29385
auto[TlIntgErrNone]	full_word	auto[1]	112788743	1			T1	7468		T2	77		T3	11530
auto[TlIntgErrCmd]	partial	auto[0]	36	1			T121	2		T122	2		T179	3
auto[TlIntgErrCmd]	partial	auto[1]	52	1			T121	2		T179	3		T178	4
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T181	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T178	1		T182	1		T180	1
auto[TlIntgErrData]	partial	auto[0]	42	1			T120	3		T121	4		T122	3
auto[TlIntgErrData]	partial	auto[1]	52	1			T120	1		T121	2		T122	2
auto[TlIntgErrData]	full_word	auto[0]	7	1			T122	1		T179	1		T183	1
auto[TlIntgErrData]	full_word	auto[1]	1	1			T121	1		-	-		-	-
auto[TlIntgErrBoth]	partial	auto[0]	41	1			T120	1		T121	2		T122	1
auto[TlIntgErrBoth]	partial	auto[1]	57	1			T120	5		T121	4		T122	1
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T121	2		T182	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T121	1		T179	1		T182	1