Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	607254	0	0
entropy_period_rd_A	2147483647	1754	0	0
intr_enable_rd_A	2147483647	2376	0	0
prefix_0_rd_A	2147483647	1726	0	0
prefix_10_rd_A	2147483647	1709	0	0
prefix_1_rd_A	2147483647	1904	0	0
prefix_2_rd_A	2147483647	1739	0	0
prefix_3_rd_A	2147483647	1840	0	0
prefix_4_rd_A	2147483647	1787	0	0
prefix_5_rd_A	2147483647	1813	0	0
prefix_6_rd_A	2147483647	1867	0	0
prefix_7_rd_A	2147483647	1881	0	0
prefix_8_rd_A	2147483647	1640	0	0
prefix_9_rd_A	2147483647	1805	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	607254	0	0
T10	308583	0	0	0
T52	302156	27691	0	0
T53	0	92764	0	0
T54	0	33022	0	0
T72	970880	0	0	0
T73	181792	0	0	0
T74	254216	0	0	0
T89	0	98159	0	0
T91	0	37659	0	0
T92	0	40964	0	0
T127	0	76724	0	0
T128	0	11510	0	0
T129	0	93775	0	0
T130	0	91813	0	0
T131	108049	0	0	0
T132	116316	0	0	0
T133	7067	0	0	0
T134	164402	0	0	0
T135	980	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1754	0	0
T70	158027	0	0	0
T91	553636	129	0	0
T92	0	118	0	0
T97	0	24	0	0
T120	0	52	0	0
T121	0	82	0	0
T146	0	15	0	0
T147	0	5	0	0
T148	0	7	0	0
T149	0	40	0	0
T150	0	6	0	0
T151	916	0	0	0
T152	202474	0	0	0
T153	86613	0	0	0
T154	63960	0	0	0
T155	3211	0	0	0
T156	319676	0	0	0
T157	1153	0	0	0
T158	1053	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2376	0	0
T70	158027	0	0	0
T91	553636	79	0	0
T92	0	62	0	0
T97	0	24	0	0
T120	0	75	0	0
T121	0	95	0	0
T123	0	24	0	0
T146	0	14	0	0
T147	0	19	0	0
T148	0	8	0	0
T151	916	0	0	0
T152	202474	0	0	0
T153	86613	0	0	0
T154	63960	0	0	0
T155	3211	0	0	0
T156	319676	0	0	0
T157	1153	0	0	0
T158	1053	0	0	0
T159	0	1	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1726	0	0
T70	158027	0	0	0
T91	553636	73	0	0
T92	0	69	0	0
T97	0	24	0	0
T120	0	44	0	0
T121	0	57	0	0
T146	0	2	0	0
T147	0	20	0	0
T148	0	3	0	0
T149	0	36	0	0
T151	916	0	0	0
T152	202474	0	0	0
T153	86613	0	0	0
T154	63960	0	0	0
T155	3211	0	0	0
T156	319676	0	0	0
T157	1153	0	0	0
T158	1053	0	0	0
T159	0	6	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1709	0	0
T70	158027	0	0	0
T91	553636	87	0	0
T92	0	95	0	0
T97	0	5	0	0
T120	0	37	0	0
T121	0	26	0	0
T146	0	17	0	0
T147	0	16	0	0
T148	0	12	0	0
T149	0	3	0	0
T151	916	0	0	0
T152	202474	0	0	0
T153	86613	0	0	0
T154	63960	0	0	0
T155	3211	0	0	0
T156	319676	0	0	0
T157	1153	0	0	0
T158	1053	0	0	0
T159	0	6	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1904	0	0
T70	158027	0	0	0
T91	553636	91	0	0
T92	0	103	0	0
T97	0	23	0	0
T120	0	47	0	0
T121	0	54	0	0
T146	0	17	0	0
T147	0	22	0	0
T148	0	6	0	0
T149	0	20	0	0
T151	916	0	0	0
T152	202474	0	0	0
T153	86613	0	0	0
T154	63960	0	0	0
T155	3211	0	0	0
T156	319676	0	0	0
T157	1153	0	0	0
T158	1053	0	0	0
T159	0	1	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1739	0	0
T70	158027	0	0	0
T91	553636	75	0	0
T92	0	103	0	0
T97	0	18	0	0
T120	0	27	0	0
T121	0	34	0	0
T146	0	18	0	0
T147	0	34	0	0
T148	0	8	0	0
T149	0	66	0	0
T151	916	0	0	0
T152	202474	0	0	0
T153	86613	0	0	0
T154	63960	0	0	0
T155	3211	0	0	0
T156	319676	0	0	0
T157	1153	0	0	0
T158	1053	0	0	0
T159	0	3	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1840	0	0
T70	158027	0	0	0
T91	553636	107	0	0
T92	0	136	0	0
T97	0	15	0	0
T120	0	25	0	0
T121	0	35	0	0
T146	0	12	0	0
T147	0	21	0	0
T148	0	6	0	0
T149	0	14	0	0
T150	0	3	0	0
T151	916	0	0	0
T152	202474	0	0	0
T153	86613	0	0	0
T154	63960	0	0	0
T155	3211	0	0	0
T156	319676	0	0	0
T157	1153	0	0	0
T158	1053	0	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1787	0	0
T70	158027	0	0	0
T91	553636	81	0	0
T92	0	133	0	0
T97	0	12	0	0
T120	0	44	0	0
T121	0	37	0	0
T146	0	16	0	0
T147	0	27	0	0
T148	0	7	0	0
T149	0	46	0	0
T151	916	0	0	0
T152	202474	0	0	0
T153	86613	0	0	0
T154	63960	0	0	0
T155	3211	0	0	0
T156	319676	0	0	0
T157	1153	0	0	0
T158	1053	0	0	0
T159	0	1	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1813	0	0
T70	158027	0	0	0
T91	553636	74	0	0
T92	0	133	0	0
T97	0	9	0	0
T120	0	31	0	0
T121	0	59	0	0
T146	0	2	0	0
T147	0	28	0	0
T148	0	6	0	0
T149	0	4	0	0
T151	916	0	0	0
T152	202474	0	0	0
T153	86613	0	0	0
T154	63960	0	0	0
T155	3211	0	0	0
T156	319676	0	0	0
T157	1153	0	0	0
T158	1053	0	0	0
T159	0	4	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1867	0	0
T70	158027	0	0	0
T91	553636	139	0	0
T92	0	109	0	0
T97	0	25	0	0
T120	0	30	0	0
T121	0	58	0	0
T146	0	11	0	0
T147	0	25	0	0
T148	0	4	0	0
T149	0	43	0	0
T151	916	0	0	0
T152	202474	0	0	0
T153	86613	0	0	0
T154	63960	0	0	0
T155	3211	0	0	0
T156	319676	0	0	0
T157	1153	0	0	0
T158	1053	0	0	0
T159	0	1	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1881	0	0
T70	158027	0	0	0
T91	553636	126	0	0
T92	0	165	0	0
T97	0	2	0	0
T120	0	30	0	0
T121	0	66	0	0
T146	0	20	0	0
T147	0	32	0	0
T148	0	11	0	0
T149	0	49	0	0
T151	916	0	0	0
T152	202474	0	0	0
T153	86613	0	0	0
T154	63960	0	0	0
T155	3211	0	0	0
T156	319676	0	0	0
T157	1153	0	0	0
T158	1053	0	0	0
T159	0	1	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1640	0	0
T70	158027	0	0	0
T91	553636	123	0	0
T92	0	95	0	0
T97	0	14	0	0
T120	0	32	0	0
T121	0	9	0	0
T146	0	21	0	0
T147	0	19	0	0
T148	0	10	0	0
T149	0	19	0	0
T151	916	0	0	0
T152	202474	0	0	0
T153	86613	0	0	0
T154	63960	0	0	0
T155	3211	0	0	0
T156	319676	0	0	0
T157	1153	0	0	0
T158	1053	0	0	0
T159	0	5	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1805	0	0
T70	158027	0	0	0
T91	553636	104	0	0
T92	0	78	0	0
T97	0	32	0	0
T120	0	32	0	0
T121	0	54	0	0
T146	0	10	0	0
T147	0	26	0	0
T148	0	9	0	0
T149	0	18	0	0
T151	916	0	0	0
T152	202474	0	0	0
T153	86613	0	0	0
T154	63960	0	0	0
T155	3211	0	0	0
T156	319676	0	0	0
T157	1153	0	0	0
T158	1053	0	0	0
T159	0	4	0	0