Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 254786026 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 200107810 1 T1 339558 T2 1425 T3 100154



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 240297886 1 T1 448803 T2 1095 T3 127753
values[0x0] 103083959 1 T1 205740 T2 485 T3 552522
values[0x1] 111511991 1 T1 224627 T2 525 T3 601131



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 198574065 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 256319771 1 T1 458953 T2 1577 T3 131666



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 1407695 1 T1 3209 T2 6 T12 12
valid_sources[0x01] 1912283 1 T1 3441 T2 10 T12 14
valid_sources[0x02] 1429962 1 T1 3387 T2 5 T12 20
valid_sources[0x03] 1981524 1 T1 3625 T2 15 T12 16
valid_sources[0x04] 1414711 1 T1 3707 T2 6 T12 22
valid_sources[0x05] 2044541 1 T1 3443 T2 6 T12 14
valid_sources[0x06] 2735561 1 T1 3308 T2 11 T12 20
valid_sources[0x07] 1405975 1 T1 3326 T2 6 T12 19
valid_sources[0x08] 1413024 1 T1 3333 T2 6 T12 21
valid_sources[0x09] 1405512 1 T1 3633 T2 2 T12 15
valid_sources[0x0a] 1401382 1 T1 3071 T2 8 T12 18
valid_sources[0x0b] 1557584 1 T1 3439 T2 8 T12 14
valid_sources[0x0c] 1397481 1 T1 3293 T2 10 T12 18
valid_sources[0x0d] 1408330 1 T1 4010 T2 8 T12 12
valid_sources[0x0e] 1549572 1 T1 3861 T2 2 T12 19
valid_sources[0x0f] 1401347 1 T1 3376 T2 8 T12 13
valid_sources[0x10] 1511866 1 T1 3459 T2 10 T12 15
valid_sources[0x11] 1407514 1 T1 3525 T2 5 T12 11
valid_sources[0x12] 1408866 1 T1 3503 T2 6 T12 19
valid_sources[0x13] 1977512 1 T1 3517 T2 17 T12 15
valid_sources[0x14] 3459493 1 T1 3403 T2 16 T12 13
valid_sources[0x15] 1408732 1 T1 3227 T2 15 T12 11
valid_sources[0x16] 2015160 1 T1 3213 T2 11 T12 18
valid_sources[0x17] 2066833 1 T1 3541 T2 9 T12 20
valid_sources[0x18] 1401324 1 T1 3649 T2 10 T12 8
valid_sources[0x19] 1432501 1 T1 3431 T2 7 T12 19
valid_sources[0x1a] 1409307 1 T1 3449 T2 7 T12 12
valid_sources[0x1b] 3830127 1 T1 3313 T2 8 T12 19
valid_sources[0x1c] 1404281 1 T1 3460 T2 6 T12 28
valid_sources[0x1d] 1409125 1 T1 3262 T2 11 T12 18
valid_sources[0x1e] 2938956 1 T1 3407 T2 9 T12 18
valid_sources[0x1f] 1403852 1 T1 3227 T2 10 T12 12
valid_sources[0x20] 1401612 1 T1 3541 T2 6 T12 19
valid_sources[0x21] 1433639 1 T1 3601 T2 8 T12 18
valid_sources[0x22] 1401987 1 T1 3800 T2 4 T12 11
valid_sources[0x23] 1450494 1 T1 3402 T2 12 T12 19
valid_sources[0x24] 1408277 1 T1 3173 T2 7 T12 16
valid_sources[0x25] 3224970 1 T1 3468 T2 5 T12 18
valid_sources[0x26] 1862150 1 T1 3423 T2 6 T12 10
valid_sources[0x27] 1402665 1 T1 3556 T2 5 T12 18
valid_sources[0x28] 1404765 1 T1 3507 T2 14 T12 22
valid_sources[0x29] 1405924 1 T1 3294 T2 8 T12 22
valid_sources[0x2a] 1408005 1 T1 3447 T2 13 T12 24
valid_sources[0x2b] 2538082 1 T1 3217 T2 12 T12 21
valid_sources[0x2c] 1640449 1 T1 3228 T2 7 T12 15
valid_sources[0x2d] 1406538 1 T1 3364 T2 10 T12 15
valid_sources[0x2e] 2257357 1 T1 3537 T2 12 T12 17
valid_sources[0x2f] 1404685 1 T1 3204 T2 10 T12 29
valid_sources[0x30] 2302140 1 T1 3450 T2 4 T12 13
valid_sources[0x31] 1410266 1 T1 3490 T2 8 T12 11
valid_sources[0x32] 1407494 1 T1 3510 T2 8 T12 18
valid_sources[0x33] 1411620 1 T1 3325 T2 8 T12 10
valid_sources[0x34] 1403517 1 T1 3057 T2 14 T12 19
valid_sources[0x35] 1407413 1 T1 3314 T2 9 T12 12
valid_sources[0x36] 1404597 1 T1 3480 T2 2 T12 17
valid_sources[0x37] 1651252 1 T1 3537 T2 4 T12 14
valid_sources[0x38] 1414042 1 T1 3560 T2 7 T12 13
valid_sources[0x39] 1405883 1 T1 3472 T2 7 T12 12
valid_sources[0x3a] 1404793 1 T1 3296 T2 13 T12 11
valid_sources[0x3b] 2074764 1 T1 3759 T2 13 T12 20
valid_sources[0x3c] 1403308 1 T1 3318 T2 7 T12 11
valid_sources[0x3d] 1411307 1 T1 3633 T2 4 T12 13
valid_sources[0x3e] 1518945 1 T1 3193 T2 5 T12 26
valid_sources[0x3f] 1860475 1 T1 3116 T2 7 T12 6
valid_sources[0x40] 1399533 1 T1 3548 T2 4 T12 16
valid_sources[0x41] 1419717 1 T1 3465 T2 12 T12 16
valid_sources[0x42] 1404044 1 T1 3550 T2 10 T12 19
valid_sources[0x43] 1409634 1 T1 3484 T2 5 T12 9
valid_sources[0x44] 2068040 1 T1 3226 T2 9 T12 12
valid_sources[0x45] 1400267 1 T1 3638 T2 11 T12 18
valid_sources[0x46] 4313514 1 T1 3263 T2 5 T12 16
valid_sources[0x47] 1630298 1 T1 3563 T2 11 T12 14
valid_sources[0x48] 2319013 1 T1 3576 T2 6 T12 18
valid_sources[0x49] 2354240 1 T1 3299 T2 10 T12 17
valid_sources[0x4a] 1407053 1 T1 3395 T2 4 T12 12
valid_sources[0x4b] 1407411 1 T1 3573 T2 8 T12 23
valid_sources[0x4c] 1404597 1 T1 3622 T2 7 T12 13
valid_sources[0x4d] 1980954 1 T1 3332 T2 3 T12 16
valid_sources[0x4e] 1415896 1 T1 3334 T2 7 T12 14
valid_sources[0x4f] 2698744 1 T1 3251 T2 18 T12 8
valid_sources[0x50] 1405202 1 T1 3566 T2 12 T12 17
valid_sources[0x51] 2320405 1 T1 3315 T2 6 T12 17
valid_sources[0x52] 1413688 1 T1 3773 T2 8 T12 19
valid_sources[0x53] 2050327 1 T1 3319 T2 8 T12 20
valid_sources[0x54] 1403818 1 T1 3463 T2 16 T12 14
valid_sources[0x55] 1404395 1 T1 3471 T2 10 T12 14
valid_sources[0x56] 1423019 1 T1 3357 T2 9 T12 18
valid_sources[0x57] 1411664 1 T1 3498 T2 6 T12 16
valid_sources[0x58] 1405914 1 T1 3282 T2 14 T12 24
valid_sources[0x59] 2531553 1 T1 3289 T2 7 T12 18
valid_sources[0x5a] 1405679 1 T1 3654 T2 11 T12 13
valid_sources[0x5b] 1401405 1 T1 3369 T2 8 T12 19
valid_sources[0x5c] 1414473 1 T1 3515 T2 10 T12 18
valid_sources[0x5d] 1428811 1 T1 3271 T2 11 T12 15
valid_sources[0x5e] 1400046 1 T1 3278 T2 7 T12 14
valid_sources[0x5f] 1408452 1 T1 3422 T2 8 T12 17
valid_sources[0x60] 1417202 1 T1 3388 T2 9 T12 21
valid_sources[0x61] 1412805 1 T1 3383 T2 3 T12 10
valid_sources[0x62] 1881057 1 T1 3190 T2 5 T12 15
valid_sources[0x63] 1403604 1 T1 3465 T2 4 T12 13
valid_sources[0x64] 3872699 1 T1 3062 T2 4 T12 67455
valid_sources[0x65] 1401552 1 T1 3461 T2 5 T12 12
valid_sources[0x66] 1408945 1 T1 3566 T2 7 T12 20
valid_sources[0x67] 1406886 1 T1 3558 T2 5 T12 13
valid_sources[0x68] 3820402 1 T1 3345 T2 12 T12 12
valid_sources[0x69] 1478423 1 T1 3147 T2 10 T12 20
valid_sources[0x6a] 1400940 1 T1 3338 T2 8 T12 17
valid_sources[0x6b] 2071773 1 T1 3515 T2 8 T12 19
valid_sources[0x6c] 1411095 1 T1 3594 T2 11 T12 20
valid_sources[0x6d] 1475293 1 T1 3324 T2 10 T12 18
valid_sources[0x6e] 1414108 1 T1 3164 T2 13 T12 9
valid_sources[0x6f] 1399647 1 T1 3225 T2 12 T12 13
valid_sources[0x70] 1408672 1 T1 3259 T2 5 T12 13
valid_sources[0x71] 1913293 1 T1 3472 T2 8 T12 18
valid_sources[0x72] 1406301 1 T1 3169 T2 8 T12 23
valid_sources[0x73] 2321240 1 T1 3250 T2 4 T12 13
valid_sources[0x74] 1426627 1 T1 3234 T2 4 T12 18
valid_sources[0x75] 2047353 1 T1 3452 T2 6 T12 20
valid_sources[0x76] 2771162 1 T1 3427 T2 12 T12 14
valid_sources[0x77] 2234761 1 T1 3641 T2 11 T12 16
valid_sources[0x78] 1400687 1 T1 3505 T2 6 T12 16
valid_sources[0x79] 1406249 1 T1 3662 T2 11 T12 19
valid_sources[0x7a] 1403553 1 T1 2915 T2 10 T12 17
valid_sources[0x7b] 1458820 1 T1 3737 T2 5 T12 14
valid_sources[0x7c] 3817998 1 T1 3171 T2 13 T12 9
valid_sources[0x7d] 1406468 1 T1 3826 T2 5 T12 19
valid_sources[0x7e] 1409258 1 T1 3234 T2 10 T12 19
valid_sources[0x7f] 4746543 1 T1 3159 T2 9 T12 12
valid_sources[0x80] 1409670 1 T1 3229 T2 15 T12 20



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 87479807 1 T1 128927 T2 709 T3 428001
values[0x0] all_enables biggest_size 60611839 1 T1 114280 T2 359 T3 310839
values[0x1] all_enables biggest_size 52016164 1 T1 96351 T2 357 T3 262703

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%