Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

256850329

1

T1

539612

T2

680

T3

142964

full_word

200237385

1

T1

339558

T2

1425

T3

100154

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	457087434	1			T1	879170		T2	2105		T3	243118
auto[TlIntgErrCmd]	96	1			T115	3		T116	5		T117	8
auto[TlIntgErrData]	94	1			T115	3		T116	5		T117	9
auto[TlIntgErrBoth]	90	1			T115	4		T116	10		T117	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

240701502

1

T1

448803

T2

1095

T3

127753

auto[1]

216386212

1

T1

430367

T2

1010

T3

115365

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	153188823	1			T1	319876		T2	386		T3	849535
auto[TlIntgErrNone]	partial	auto[1]	103661240	1			T1	219736		T2	294		T3	580111
auto[TlIntgErrNone]	full_word	auto[0]	87512558	1			T1	128927		T2	709		T3	428001
auto[TlIntgErrNone]	full_word	auto[1]	112724813	1			T1	210631		T2	716		T3	573542
auto[TlIntgErrCmd]	partial	auto[0]	39	1			T115	1		T116	3		T117	2
auto[TlIntgErrCmd]	partial	auto[1]	51	1			T115	2		T116	1		T117	5
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T117	1		T182	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T116	1		T181	1		T182	1
auto[TlIntgErrData]	partial	auto[0]	40	1			T116	1		T117	5		T183	4
auto[TlIntgErrData]	partial	auto[1]	49	1			T115	2		T116	3		T117	4
auto[TlIntgErrData]	full_word	auto[0]	2	1			T115	1		T116	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	3	1			T145	1		T184	1		T185	1
auto[TlIntgErrBoth]	partial	auto[0]	36	1			T115	2		T116	4		T181	3
auto[TlIntgErrBoth]	partial	auto[1]	51	1			T115	2		T116	6		T117	3
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T183	1		T186	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	1	1			T182	1		-	-		-	-