Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	477915	0	0
entropy_period_rd_A	2147483647	1090	0	0
intr_enable_rd_A	2147483647	1543	0	0
prefix_0_rd_A	2147483647	1013	0	0
prefix_10_rd_A	2147483647	1062	0	0
prefix_1_rd_A	2147483647	1068	0	0
prefix_2_rd_A	2147483647	957	0	0
prefix_3_rd_A	2147483647	981	0	0
prefix_4_rd_A	2147483647	1184	0	0
prefix_5_rd_A	2147483647	997	0	0
prefix_6_rd_A	2147483647	1077	0	0
prefix_7_rd_A	2147483647	1010	0	0
prefix_8_rd_A	2147483647	1120	0	0
prefix_9_rd_A	2147483647	1032	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	477915	0	0
T10	565419	0	0	0
T49	203014	0	0	0
T54	911431	12283	0	0
T55	0	47295	0	0
T56	0	31485	0	0
T88	0	60710	0	0
T94	0	113634	0	0
T95	0	50187	0	0
T121	0	66091	0	0
T122	0	65610	0	0
T123	0	27119	0	0
T124	0	105	0	0
T125	111047	0	0	0
T126	650001	0	0	0
T127	192551	0	0	0
T128	186469	0	0	0
T129	897318	0	0	0
T130	136547	0	0	0
T131	898065	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1090	0	0
T88	651850	224	0	0
T107	0	13	0	0
T140	0	49	0	0
T141	0	8	0	0
T142	0	6	0	0
T143	0	13	0	0
T144	0	38	0	0
T145	0	49	0	0
T146	0	228	0	0
T147	0	3	0	0
T148	14539	0	0	0
T149	100883	0	0	0
T150	134593	0	0	0
T151	25576	0	0	0
T152	151541	0	0	0
T153	148678	0	0	0
T154	7133	0	0	0
T155	393989	0	0	0
T156	16727	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1543	0	0
T88	651850	178	0	0
T140	0	54	0	0
T141	0	14	0	0
T142	0	3	0	0
T143	0	13	0	0
T144	0	39	0	0
T145	0	49	0	0
T148	14539	0	0	0
T149	100883	0	0	0
T150	134593	0	0	0
T151	25576	0	0	0
T152	151541	0	0	0
T153	148678	0	0	0
T154	7133	0	0	0
T155	393989	0	0	0
T156	16727	0	0	0
T157	0	9	0	0
T158	0	14	0	0
T159	0	9	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1013	0	0
T88	651850	108	0	0
T107	0	18	0	0
T140	0	78	0	0
T142	0	2	0	0
T143	0	11	0	0
T144	0	20	0	0
T145	0	29	0	0
T146	0	204	0	0
T147	0	5	0	0
T148	14539	0	0	0
T149	100883	0	0	0
T150	134593	0	0	0
T151	25576	0	0	0
T152	151541	0	0	0
T153	148678	0	0	0
T154	7133	0	0	0
T155	393989	0	0	0
T156	16727	0	0	0
T160	0	51	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1062	0	0
T88	651850	147	0	0
T107	0	15	0	0
T140	0	67	0	0
T142	0	9	0	0
T143	0	7	0	0
T144	0	25	0	0
T145	0	29	0	0
T146	0	201	0	0
T147	0	31	0	0
T148	14539	0	0	0
T149	100883	0	0	0
T150	134593	0	0	0
T151	25576	0	0	0
T152	151541	0	0	0
T153	148678	0	0	0
T154	7133	0	0	0
T155	393989	0	0	0
T156	16727	0	0	0
T160	0	46	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1068	0	0
T88	651850	173	0	0
T107	0	6	0	0
T140	0	35	0	0
T141	0	18	0	0
T142	0	6	0	0
T143	0	10	0	0
T144	0	25	0	0
T145	0	33	0	0
T146	0	257	0	0
T147	0	19	0	0
T148	14539	0	0	0
T149	100883	0	0	0
T150	134593	0	0	0
T151	25576	0	0	0
T152	151541	0	0	0
T153	148678	0	0	0
T154	7133	0	0	0
T155	393989	0	0	0
T156	16727	0	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	957	0	0
T88	651850	105	0	0
T107	0	14	0	0
T140	0	44	0	0
T141	0	7	0	0
T142	0	1	0	0
T143	0	12	0	0
T144	0	20	0	0
T145	0	33	0	0
T146	0	200	0	0
T147	0	33	0	0
T148	14539	0	0	0
T149	100883	0	0	0
T150	134593	0	0	0
T151	25576	0	0	0
T152	151541	0	0	0
T153	148678	0	0	0
T154	7133	0	0	0
T155	393989	0	0	0
T156	16727	0	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	981	0	0
T88	651850	153	0	0
T107	0	22	0	0
T140	0	15	0	0
T141	0	6	0	0
T142	0	8	0	0
T143	0	9	0	0
T144	0	15	0	0
T145	0	41	0	0
T146	0	219	0	0
T147	0	16	0	0
T148	14539	0	0	0
T149	100883	0	0	0
T150	134593	0	0	0
T151	25576	0	0	0
T152	151541	0	0	0
T153	148678	0	0	0
T154	7133	0	0	0
T155	393989	0	0	0
T156	16727	0	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1184	0	0
T88	651850	229	0	0
T107	0	16	0	0
T140	0	53	0	0
T141	0	2	0	0
T143	0	10	0	0
T144	0	17	0	0
T145	0	35	0	0
T146	0	216	0	0
T147	0	34	0	0
T148	14539	0	0	0
T149	100883	0	0	0
T150	134593	0	0	0
T151	25576	0	0	0
T152	151541	0	0	0
T153	148678	0	0	0
T154	7133	0	0	0
T155	393989	0	0	0
T156	16727	0	0	0
T160	0	23	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	997	0	0
T88	651850	184	0	0
T107	0	10	0	0
T140	0	25	0	0
T141	0	4	0	0
T142	0	5	0	0
T143	0	4	0	0
T144	0	39	0	0
T145	0	42	0	0
T146	0	176	0	0
T147	0	1	0	0
T148	14539	0	0	0
T149	100883	0	0	0
T150	134593	0	0	0
T151	25576	0	0	0
T152	151541	0	0	0
T153	148678	0	0	0
T154	7133	0	0	0
T155	393989	0	0	0
T156	16727	0	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1077	0	0
T88	651850	141	0	0
T107	0	15	0	0
T140	0	39	0	0
T141	0	7	0	0
T142	0	8	0	0
T143	0	14	0	0
T144	0	29	0	0
T145	0	32	0	0
T146	0	236	0	0
T147	0	40	0	0
T148	14539	0	0	0
T149	100883	0	0	0
T150	134593	0	0	0
T151	25576	0	0	0
T152	151541	0	0	0
T153	148678	0	0	0
T154	7133	0	0	0
T155	393989	0	0	0
T156	16727	0	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1010	0	0
T88	651850	163	0	0
T107	0	11	0	0
T140	0	26	0	0
T141	0	2	0	0
T142	0	5	0	0
T143	0	5	0	0
T144	0	18	0	0
T145	0	43	0	0
T146	0	219	0	0
T147	0	6	0	0
T148	14539	0	0	0
T149	100883	0	0	0
T150	134593	0	0	0
T151	25576	0	0	0
T152	151541	0	0	0
T153	148678	0	0	0
T154	7133	0	0	0
T155	393989	0	0	0
T156	16727	0	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1120	0	0
T88	651850	166	0	0
T107	0	4	0	0
T140	0	4	0	0
T141	0	5	0	0
T142	0	8	0	0
T143	0	7	0	0
T144	0	30	0	0
T145	0	25	0	0
T146	0	238	0	0
T147	0	20	0	0
T148	14539	0	0	0
T149	100883	0	0	0
T150	134593	0	0	0
T151	25576	0	0	0
T152	151541	0	0	0
T153	148678	0	0	0
T154	7133	0	0	0
T155	393989	0	0	0
T156	16727	0	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1032	0	0
T88	651850	170	0	0
T107	0	18	0	0
T140	0	16	0	0
T142	0	7	0	0
T143	0	15	0	0
T144	0	22	0	0
T145	0	32	0	0
T146	0	212	0	0
T147	0	10	0	0
T148	14539	0	0	0
T149	100883	0	0	0
T150	134593	0	0	0
T151	25576	0	0	0
T152	151541	0	0	0
T153	148678	0	0	0
T154	7133	0	0	0
T155	393989	0	0	0
T156	16727	0	0	0
T161	0	3	0	0