Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

255961507

1

T1

13

T2

10126

T3

66977

full_word

200209886

1

T1

175

T2

140060

T3

113038

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	456171073	1			T1	188		T2	150186		T3	180015
auto[TlIntgErrCmd]	104	1			T114	7		T115	3		T116	4
auto[TlIntgErrData]	114	1			T114	5		T115	3		T116	4
auto[TlIntgErrBoth]	102	1			T114	8		T115	4		T116	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

239685616

1

T1

93

T2

42143

T3

120964

auto[1]

216485777

1

T1

95

T2

108043

T3

59051

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	152664243	1			T1	4		T2	8350		T3	40563
auto[TlIntgErrNone]	partial	auto[1]	103296979	1			T1	9		T2	1776		T3	26414
auto[TlIntgErrNone]	full_word	auto[0]	87021224	1			T1	89		T2	33793		T3	80401
auto[TlIntgErrNone]	full_word	auto[1]	113188627	1			T1	86		T2	106267		T3	32637
auto[TlIntgErrCmd]	partial	auto[0]	42	1			T114	4		T115	2		T192	2
auto[TlIntgErrCmd]	partial	auto[1]	54	1			T114	3		T116	3		T192	2
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T193	1		T199	1		T200	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T115	1		T116	1		T160	1
auto[TlIntgErrData]	partial	auto[0]	53	1			T114	2		T115	1		T116	2
auto[TlIntgErrData]	partial	auto[1]	48	1			T114	2		T115	2		T116	1
auto[TlIntgErrData]	full_word	auto[0]	7	1			T114	1		T116	1		T193	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T197	1		T193	1		T194	2
auto[TlIntgErrBoth]	partial	auto[0]	36	1			T114	3		T115	2		T192	2
auto[TlIntgErrBoth]	partial	auto[1]	52	1			T114	3		T115	1		T116	2
auto[TlIntgErrBoth]	full_word	auto[0]	8	1			T114	1		T115	1		T192	2
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T114	1		T197	1		T195	2