Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	471351	0	0
entropy_period_rd_A	2147483647	1589	0	0
intr_enable_rd_A	2147483647	2071	0	0
prefix_0_rd_A	2147483647	1650	0	0
prefix_10_rd_A	2147483647	1609	0	0
prefix_1_rd_A	2147483647	1468	0	0
prefix_2_rd_A	2147483647	1492	0	0
prefix_3_rd_A	2147483647	1488	0	0
prefix_4_rd_A	2147483647	1396	0	0
prefix_5_rd_A	2147483647	1442	0	0
prefix_6_rd_A	2147483647	1365	0	0
prefix_7_rd_A	2147483647	1526	0	0
prefix_8_rd_A	2147483647	1437	0	0
prefix_9_rd_A	2147483647	1549	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	471351	0	0
T51	108600	147747	0	0
T52	642846	86125	0	0
T53	0	38873	0	0
T55	22151	0	0	0
T93	0	39923	0	0
T114	0	4	0	0
T121	0	49511	0	0
T122	0	20128	0	0
T123	0	43651	0	0
T124	0	42446	0	0
T125	0	313	0	0
T126	176944	0	0	0
T127	9348	0	0	0
T128	331905	0	0	0
T129	195725	0	0	0
T130	210057	0	0	0
T131	16346	0	0	0
T132	219927	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1589	0	0
T93	487857	104	0	0
T100	0	79	0	0
T141	0	19	0	0
T142	0	2	0	0
T143	0	202	0	0
T144	0	9	0	0
T145	0	5	0	0
T146	0	22	0	0
T147	0	5	0	0
T148	0	2	0	0
T149	651208	0	0	0
T150	127252	0	0	0
T151	278821	0	0	0
T152	136835	0	0	0
T153	408660	0	0	0
T154	5128	0	0	0
T155	3556	0	0	0
T156	192932	0	0	0
T157	22191	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2071	0	0
T93	487857	66	0	0
T107	0	5	0	0
T119	0	8	0	0
T141	0	6	0	0
T142	0	5	0	0
T143	0	233	0	0
T144	0	13	0	0
T145	0	30	0	0
T149	651208	0	0	0
T150	127252	0	0	0
T151	278821	0	0	0
T152	136835	0	0	0
T153	408660	0	0	0
T154	5128	0	0	0
T155	3556	0	0	0
T156	192932	0	0	0
T157	22191	0	0	0
T158	0	2	0	0
T159	0	24	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1650	0	0
T93	487857	125	0	0
T100	0	64	0	0
T107	0	10	0	0
T141	0	38	0	0
T143	0	281	0	0
T144	0	4	0	0
T145	0	13	0	0
T146	0	26	0	0
T147	0	7	0	0
T148	0	31	0	0
T149	651208	0	0	0
T150	127252	0	0	0
T151	278821	0	0	0
T152	136835	0	0	0
T153	408660	0	0	0
T154	5128	0	0	0
T155	3556	0	0	0
T156	192932	0	0	0
T157	22191	0	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1609	0	0
T93	487857	81	0	0
T100	0	60	0	0
T107	0	2	0	0
T141	0	25	0	0
T142	0	7	0	0
T143	0	226	0	0
T145	0	12	0	0
T146	0	9	0	0
T147	0	3	0	0
T148	0	48	0	0
T149	651208	0	0	0
T150	127252	0	0	0
T151	278821	0	0	0
T152	136835	0	0	0
T153	408660	0	0	0
T154	5128	0	0	0
T155	3556	0	0	0
T156	192932	0	0	0
T157	22191	0	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1468	0	0
T93	487857	126	0	0
T100	0	49	0	0
T141	0	5	0	0
T143	0	206	0	0
T145	0	6	0	0
T146	0	11	0	0
T148	0	11	0	0
T149	651208	0	0	0
T150	127252	0	0	0
T151	278821	0	0	0
T152	136835	0	0	0
T153	408660	0	0	0
T154	5128	0	0	0
T155	3556	0	0	0
T156	192932	0	0	0
T157	22191	0	0	0
T160	0	78	0	0
T161	0	27	0	0
T162	0	68	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1492	0	0
T93	487857	109	0	0
T100	0	32	0	0
T107	0	7	0	0
T141	0	14	0	0
T143	0	255	0	0
T144	0	2	0	0
T145	0	13	0	0
T146	0	38	0	0
T147	0	1	0	0
T148	0	11	0	0
T149	651208	0	0	0
T150	127252	0	0	0
T151	278821	0	0	0
T152	136835	0	0	0
T153	408660	0	0	0
T154	5128	0	0	0
T155	3556	0	0	0
T156	192932	0	0	0
T157	22191	0	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1488	0	0
T93	487857	117	0	0
T100	0	57	0	0
T107	0	7	0	0
T141	0	3	0	0
T143	0	225	0	0
T144	0	6	0	0
T145	0	1	0	0
T146	0	6	0	0
T147	0	5	0	0
T148	0	30	0	0
T149	651208	0	0	0
T150	127252	0	0	0
T151	278821	0	0	0
T152	136835	0	0	0
T153	408660	0	0	0
T154	5128	0	0	0
T155	3556	0	0	0
T156	192932	0	0	0
T157	22191	0	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1396	0	0
T93	487857	117	0	0
T100	0	47	0	0
T107	0	4	0	0
T141	0	19	0	0
T142	0	4	0	0
T143	0	253	0	0
T145	0	11	0	0
T146	0	2	0	0
T147	0	4	0	0
T148	0	14	0	0
T149	651208	0	0	0
T150	127252	0	0	0
T151	278821	0	0	0
T152	136835	0	0	0
T153	408660	0	0	0
T154	5128	0	0	0
T155	3556	0	0	0
T156	192932	0	0	0
T157	22191	0	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1442	0	0
T93	487857	141	0	0
T100	0	44	0	0
T107	0	3	0	0
T141	0	7	0	0
T143	0	217	0	0
T145	0	13	0	0
T146	0	8	0	0
T147	0	1	0	0
T149	651208	0	0	0
T150	127252	0	0	0
T151	278821	0	0	0
T152	136835	0	0	0
T153	408660	0	0	0
T154	5128	0	0	0
T155	3556	0	0	0
T156	192932	0	0	0
T157	22191	0	0	0
T160	0	89	0	0
T161	0	18	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1365	0	0
T93	487857	65	0	0
T100	0	48	0	0
T107	0	9	0	0
T141	0	34	0	0
T143	0	223	0	0
T144	0	8	0	0
T145	0	6	0	0
T146	0	43	0	0
T147	0	2	0	0
T148	0	21	0	0
T149	651208	0	0	0
T150	127252	0	0	0
T151	278821	0	0	0
T152	136835	0	0	0
T153	408660	0	0	0
T154	5128	0	0	0
T155	3556	0	0	0
T156	192932	0	0	0
T157	22191	0	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1526	0	0
T93	487857	76	0	0
T100	0	74	0	0
T107	0	2	0	0
T141	0	49	0	0
T142	0	1	0	0
T143	0	273	0	0
T144	0	2	0	0
T145	0	15	0	0
T146	0	30	0	0
T147	0	5	0	0
T149	651208	0	0	0
T150	127252	0	0	0
T151	278821	0	0	0
T152	136835	0	0	0
T153	408660	0	0	0
T154	5128	0	0	0
T155	3556	0	0	0
T156	192932	0	0	0
T157	22191	0	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1437	0	0
T93	487857	88	0	0
T100	0	60	0	0
T107	0	11	0	0
T141	0	7	0	0
T142	0	3	0	0
T143	0	224	0	0
T145	0	8	0	0
T146	0	30	0	0
T147	0	7	0	0
T148	0	10	0	0
T149	651208	0	0	0
T150	127252	0	0	0
T151	278821	0	0	0
T152	136835	0	0	0
T153	408660	0	0	0
T154	5128	0	0	0
T155	3556	0	0	0
T156	192932	0	0	0
T157	22191	0	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1549	0	0
T93	487857	82	0	0
T107	0	1	0	0
T133	0	7	0	0
T141	0	43	0	0
T142	0	9	0	0
T143	0	218	0	0
T145	0	10	0	0
T146	0	11	0	0
T147	0	9	0	0
T148	0	12	0	0
T149	651208	0	0	0
T150	127252	0	0	0
T151	278821	0	0	0
T152	136835	0	0	0
T153	408660	0	0	0
T154	5128	0	0	0
T155	3556	0	0	0
T156	192932	0	0	0
T157	22191	0	0	0