Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

256713018

1

T1

15146

T2

710

T3

46

full_word

201249161

1

T1

29030

T2

1412

T3

204

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	457961859	1			T1	44176		T2	2122		T3	250
auto[TlIntgErrCmd]	103	1			T101	4		T102	3		T103	5
auto[TlIntgErrData]	98	1			T101	8		T102	2		T103	5
auto[TlIntgErrBoth]	119	1			T101	8		T102	5		T103	10

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

240109143

1

T1

30367

T2

1105

T3

38

auto[1]

217853036

1

T1

13809

T2

1017

T3

212

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	152819828	1			T1	9406		T2	411		T3	30
auto[TlIntgErrNone]	partial	auto[1]	103892901	1			T1	5740		T2	299		T3	16
auto[TlIntgErrNone]	full_word	auto[0]	87289183	1			T1	20961		T2	694		T3	8
auto[TlIntgErrNone]	full_word	auto[1]	113959947	1			T1	8069		T2	718		T3	196
auto[TlIntgErrCmd]	partial	auto[0]	35	1			T101	2		T103	1		T169	1
auto[TlIntgErrCmd]	partial	auto[1]	58	1			T101	2		T102	1		T103	4
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T102	1		T173	1		T174	1
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T102	1		T136	1		T175	1
auto[TlIntgErrData]	partial	auto[0]	41	1			T101	4		T102	1		T103	3
auto[TlIntgErrData]	partial	auto[1]	46	1			T101	4		T102	1		T103	2
auto[TlIntgErrData]	full_word	auto[0]	2	1			T170	1		T171	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	9	1			T169	1		T173	1		T175	2
auto[TlIntgErrBoth]	partial	auto[0]	46	1			T101	5		T102	2		T103	4
auto[TlIntgErrBoth]	partial	auto[1]	63	1			T101	3		T102	2		T103	4
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T102	1		T176	1		T170	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T103	2		T173	1		T177	1