Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	604036	0	0
entropy_period_rd_A	2147483647	1271	0	0
intr_enable_rd_A	2147483647	1881	0	0
prefix_0_rd_A	2147483647	1334	0	0
prefix_10_rd_A	2147483647	1208	0	0
prefix_1_rd_A	2147483647	1147	0	0
prefix_2_rd_A	2147483647	1227	0	0
prefix_3_rd_A	2147483647	1196	0	0
prefix_4_rd_A	2147483647	1211	0	0
prefix_5_rd_A	2147483647	1189	0	0
prefix_6_rd_A	2147483647	1271	0	0
prefix_7_rd_A	2147483647	1218	0	0
prefix_8_rd_A	2147483647	1207	0	0
prefix_9_rd_A	2147483647	1256	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	604036	0	0
T5	4212	0	0	0
T6	3292	0	0	0
T13	334297	33130	0	0
T14	158447	0	0	0
T15	22560	0	0	0
T16	208700	0	0	0
T17	42083	0	0	0
T18	291397	0	0	0
T19	134225	0	0	0
T27	0	41762	0	0
T44	0	30142	0	0
T76	428855	0	0	0
T79	0	118023	0	0
T107	0	29903	0	0
T108	0	24394	0	0
T109	0	54040	0	0
T110	0	99496	0	0
T111	0	75816	0	0
T112	0	93741	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1271	0	0
T82	3899	1	0	0
T85	12233	65	0	0
T102	12996	50	0	0
T131	2918	16	0	0
T132	1914	9	0	0
T133	25964	192	0	0
T134	4827	9	0	0
T135	2703	8	0	0
T136	12436	57	0	0
T137	9832	8	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1881	0	0
T82	3899	10	0	0
T104	1593	10	0	0
T105	2067	13	0	0
T131	2918	24	0	0
T138	1123	6	0	0
T139	1613	19	0	0
T140	1033	4	0	0
T141	1819	27	0	0
T142	1065	16	0	0
T143	1009	21	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1334	0	0
T82	3899	2	0	0
T85	12233	40	0	0
T102	12996	39	0	0
T131	2918	4	0	0
T133	25964	251	0	0
T134	4827	3	0	0
T135	2703	14	0	0
T136	12436	56	0	0
T137	9832	20	0	0
T144	1493	8	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1208	0	0
T82	3899	15	0	0
T85	12233	64	0	0
T102	12996	24	0	0
T131	2918	11	0	0
T133	25964	225	0	0
T135	2703	5	0	0
T136	12436	58	0	0
T137	9832	43	0	0
T145	4917	15	0	0
T146	8027	7	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1147	0	0
T82	3899	7	0	0
T85	12233	35	0	0
T102	12996	28	0	0
T131	2918	2	0	0
T132	1914	5	0	0
T133	25964	260	0	0
T134	4827	6	0	0
T135	2703	5	0	0
T136	12436	35	0	0
T137	9832	11	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1227	0	0
T82	3899	5	0	0
T85	12233	49	0	0
T102	12996	22	0	0
T131	2918	5	0	0
T133	25964	205	0	0
T134	4827	8	0	0
T135	2703	1	0	0
T136	12436	46	0	0
T137	9832	18	0	0
T144	1493	3	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1196	0	0
T82	3899	9	0	0
T85	12233	39	0	0
T102	12996	26	0	0
T131	2918	17	0	0
T132	1914	6	0	0
T133	25964	212	0	0
T134	4827	3	0	0
T135	2703	9	0	0
T136	12436	44	0	0
T137	9832	15	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1211	0	0
T82	3899	6	0	0
T85	12233	67	0	0
T102	12996	38	0	0
T131	2918	12	0	0
T133	25964	207	0	0
T135	2703	6	0	0
T136	12436	54	0	0
T137	9832	48	0	0
T145	4917	9	0	0
T147	13481	4	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1189	0	0
T82	3899	10	0	0
T85	12233	49	0	0
T102	12996	34	0	0
T131	2918	10	0	0
T133	25964	246	0	0
T134	4827	6	0	0
T136	12436	34	0	0
T137	9832	24	0	0
T145	4917	6	0	0
T146	8027	6	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1271	0	0
T82	3899	6	0	0
T85	12233	54	0	0
T102	12996	45	0	0
T131	2918	14	0	0
T133	25964	193	0	0
T134	4827	9	0	0
T135	2703	5	0	0
T136	12436	31	0	0
T137	9832	27	0	0
T144	1493	2	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1218	0	0
T82	3899	4	0	0
T85	12233	40	0	0
T102	12996	45	0	0
T131	2918	6	0	0
T133	25964	203	0	0
T134	4827	5	0	0
T136	12436	31	0	0
T137	9832	8	0	0
T146	8027	6	0	0
T148	4866	7	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1207	0	0
T82	3899	10	0	0
T85	12233	54	0	0
T102	12996	46	0	0
T131	2918	11	0	0
T133	25964	202	0	0
T135	2703	9	0	0
T136	12436	47	0	0
T137	9832	26	0	0
T145	4917	5	0	0
T146	8027	7	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1256	0	0
T82	3899	5	0	0
T85	12233	55	0	0
T102	12996	44	0	0
T131	2918	6	0	0
T132	1914	7	0	0
T133	25964	208	0	0
T134	4827	2	0	0
T135	2703	12	0	0
T136	12436	35	0	0
T137	9832	37	0	0