Module Definition
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Module Instance : tb.dut.u_tlul_adapter_msgfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.42 98.53 77.78 80.77 84.62


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.10 87.07 74.69 77.38 81.25


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.24 96.27 93.33 100.00 100.00 93.85 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_err 100.00 100.00 100.00 100.00 100.00
u_reqfifo 88.33 95.00 75.00 83.33 100.00
u_rsp_gen 91.67 83.33 100.00
u_rspfifo 69.33 91.43 57.14 68.75 60.00
u_sram_byte 100.00 100.00 100.00
u_sramreqfifo 65.86 86.11 54.84 62.50 60.00
u_tlul_data_integ_enc_data 0.00 0.00
u_tlul_data_integ_enc_instr 0.00 0.00



Module Instance : tb.dut.u_staterd.u_tlul_adapter

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.34 98.59 82.46 92.31 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.66 89.34 81.51 87.78 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
90.00 100.00 70.00 100.00 u_staterd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_err 100.00 100.00 100.00 100.00 100.00
u_reqfifo 88.33 95.00 75.00 83.33 100.00
u_rsp_gen 91.67 83.33 100.00
u_rspfifo 89.32 95.00 77.27 85.00 100.00
u_sram_byte 100.00 100.00 100.00
u_sramreqfifo 87.64 95.00 72.22 83.33 100.00
u_tlul_data_integ_enc_data 0.00 0.00
u_tlul_data_integ_enc_instr 0.00 0.00

Line Coverage for Module : tlul_adapter_sram ( parameter SramAw=9,SramDw=32,Outstanding=1,SramBusBankAW=12,ByteAccess=1,ErrOnWrite=0,ErrOnRead=1,CmdIntgCheck=0,EnableRspIntgGen=0,EnableDataIntgGen=0,EnableDataIntgPt=0,SecFifoPtr=0,EnableReadback=0,DataXorAddr=0,WidthMult=1,DataOutW=32,DataBitWidth=2,WoffsetWidth=1,DataWidth=32 )
Line Coverage for Module self-instances :
SCORELINE
85.42 98.53
tb.dut.u_tlul_adapter_msgfifo

Line No.TotalCoveredPercent
TOTAL686798.53
CONT_ASSIGN10700
CONT_ASSIGN11400
ALWAYS12933100.00
CONT_ASSIGN13811100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN16211100.00
CONT_ASSIGN17611100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN27411100.00
CONT_ASSIGN27511100.00
CONT_ASSIGN27611100.00
ALWAYS2818787.50
ALWAYS30166100.00
CONT_ASSIGN31511100.00
CONT_ASSIGN31911100.00
CONT_ASSIGN33811100.00
CONT_ASSIGN34311100.00
CONT_ASSIGN34911100.00
CONT_ASSIGN36111100.00
ALWAYS36433100.00
CONT_ASSIGN37111100.00
CONT_ASSIGN39211100.00
CONT_ASSIGN39311100.00
CONT_ASSIGN39411100.00
CONT_ASSIGN39511100.00
ALWAYS42566100.00
ALWAYS43755100.00
CONT_ASSIGN45211100.00
CONT_ASSIGN45311100.00
CONT_ASSIGN45411100.00
CONT_ASSIGN45811100.00
CONT_ASSIGN45911100.00
CONT_ASSIGN46111100.00
CONT_ASSIGN46211100.00
CONT_ASSIGN46911100.00
CONT_ASSIGN47211100.00
CONT_ASSIGN47611100.00
CONT_ASSIGN47700
CONT_ASSIGN47900
CONT_ASSIGN48111100.00
CONT_ASSIGN49000
ALWAYS52133100.00
CONT_ASSIGN52711100.00
CONT_ASSIGN53011100.00
CONT_ASSIGN53511100.00
CONT_ASSIGN54000
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
107 unreachable
114 unreachable
129 1 1
130 1 1
131 1 1
132 unreachable
MISSING_ELSE
138 1 1
144 1 1
151 1 1
162 1 1
176 1 1
188 1 1
274 1 1
275 1 1
276 1 1
281 1 1
283 1 1
284 1 1
286 1 1
287 1 1
288 0 1
291 1 1
294 1 1
301 1 1
303 1 1
304 1 1
305 1 1
307 1 1
310 1 1
315 1 1
319 1 1
338 1 1
343 1 1
349 1 1
361 1 1
364 1 1
365 1 1
367 1 1
371 1 1
392 1 1
393 1 1
394 1 1
395 1 1
425 1 1
426 1 1
428 1 1
429 1 1
430 1 1
431 1 1
MISSING_ELSE
437 1 1
438 1 1
440 1 1
441 1 1
442 1 1
MISSING_ELSE
452 1 1
453 1 1
454 1 1
458 1 1
459 1 1
461 1 1
462 1 1
469 1 1
472 1 1
476 1 1
477 unreachable
479 unreachable
481 1 1
490 unreachable
521 1 1
522 1 1
523 1 1
527 1 1
530 1 1
535 1 1
540 unreachable


Line Coverage for Module : tlul_adapter_sram ( parameter SramAw=7,SramDw=32,Outstanding=1,SramBusBankAW=12,ByteAccess=1,ErrOnWrite=1,ErrOnRead=0,CmdIntgCheck=0,EnableRspIntgGen=0,EnableDataIntgGen=0,EnableDataIntgPt=0,SecFifoPtr=0,EnableReadback=0,DataXorAddr=0,WidthMult=1,DataOutW=32,DataBitWidth=2,WoffsetWidth=1,DataWidth=32 )
Line Coverage for Module self-instances :
SCORELINE
93.34 98.59
tb.dut.u_staterd.u_tlul_adapter

Line No.TotalCoveredPercent
TOTAL717098.59
CONT_ASSIGN10700
CONT_ASSIGN11400
ALWAYS12933100.00
CONT_ASSIGN13811100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN17611100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN27411100.00
CONT_ASSIGN27511100.00
CONT_ASSIGN27611100.00
ALWAYS2818787.50
ALWAYS30166100.00
CONT_ASSIGN31511100.00
CONT_ASSIGN31911100.00
CONT_ASSIGN33811100.00
CONT_ASSIGN34311100.00
CONT_ASSIGN34911100.00
CONT_ASSIGN36111100.00
ALWAYS36433100.00
CONT_ASSIGN37111100.00
CONT_ASSIGN39211100.00
CONT_ASSIGN39311100.00
CONT_ASSIGN39411100.00
CONT_ASSIGN39511100.00
ALWAYS42566100.00
ALWAYS43755100.00
CONT_ASSIGN45211100.00
CONT_ASSIGN45311100.00
CONT_ASSIGN45411100.00
CONT_ASSIGN45811100.00
CONT_ASSIGN45911100.00
CONT_ASSIGN46111100.00
CONT_ASSIGN46211100.00
CONT_ASSIGN46911100.00
CONT_ASSIGN47211100.00
CONT_ASSIGN47611100.00
CONT_ASSIGN47711100.00
CONT_ASSIGN47911100.00
CONT_ASSIGN48111100.00
CONT_ASSIGN49011100.00
ALWAYS52133100.00
CONT_ASSIGN52711100.00
CONT_ASSIGN53011100.00
CONT_ASSIGN53511100.00
CONT_ASSIGN54000
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
107 unreachable
114 unreachable
129 1 1
130 1 1
131 1 1
132 unreachable
MISSING_ELSE
138 1 1
144 1 1
151 1 1
156 1 1
176 1 1
188 1 1
274 1 1
275 1 1
276 1 1
281 1 1
283 1 1
284 1 1
286 1 1
287 1 1
288 1 1
291 0 1
294 1 1
301 1 1
303 1 1
304 1 1
305 1 1
307 1 1
310 1 1
315 1 1
319 1 1
338 1 1
343 1 1
349 1 1
361 1 1
364 1 1
365 1 1
367 1 1
371 1 1
392 1 1
393 1 1
394 1 1
395 1 1
425 1 1
426 1 1
428 1 1
429 1 1
430 1 1
431 1 1
MISSING_ELSE
437 1 1
438 1 1
440 1 1
441 1 1
442 1 1
MISSING_ELSE
452 1 1
453 1 1
454 1 1
458 1 1
459 1 1
461 1 1
462 1 1
469 1 1
472 1 1
476 1 1
477 1 1
479 1 1
481 1 1
490 1 1
521 1 1
522 1 1
523 1 1
527 1 1
530 1 1
535 1 1
540 unreachable


Cond Coverage for Module : tlul_adapter_sram ( parameter SramAw=9,SramDw=32,Outstanding=1,SramBusBankAW=12,ByteAccess=1,ErrOnWrite=0,ErrOnRead=1,CmdIntgCheck=0,EnableRspIntgGen=0,EnableDataIntgGen=0,EnableDataIntgPt=0,SecFifoPtr=0,EnableReadback=0,DataXorAddr=0,WidthMult=1,DataOutW=32,DataBitWidth=2,WoffsetWidth=1,DataWidth=32 )
Cond Coverage for Module self-instances :
SCORECOND
85.42 77.78
tb.dut.u_tlul_adapter_msgfifo

TotalCoveredPercent
Conditions1088477.78
Logical1088477.78
Non-Logical00
Event00

 LINE       114
 EXPRESSION (readback_error | readback_error_q)
             -------1------   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10Unreachable

 LINE       131
 EXPRESSION (intg_error || rsp_fifo_error || sramreqfifo_error || reqfifo_error)
             -----1----    -------2------    --------3--------    ------4------
-1--2--3--4-StatusTests
0000CoveredT1,T2,T3
0001Unreachable
0010Unreachable
0100Unreachable
1000Unreachable

 LINE       138
 EXPRESSION (intg_error | rsp_fifo_error | sramreqfifo_error | reqfifo_error | intg_error_q)
             -----1----   -------2------   --------3--------   ------4------   ------5-----
-1--2--3--4--5-StatusTests
00000CoveredT1,T2,T3
00001Not Covered
00010Unreachable
00100Unreachable
01000Unreachable
10000Unreachable

 LINE       144
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? (((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0)) : 1'b0)
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       144
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       144
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       144
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       162
 EXPRESSION (tl_i.a_opcode == Get)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       176
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----
-1--2--3--4--5--6-StatusTests
000000CoveredT1,T2,T4
000001Unreachable
000010CoveredT1,T2,T3
000100Not Covered
001000CoveredT13,T27,T44
010000Unreachable
100000Not Covered

 LINE       274
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T4
11CoveredT1,T2,T4

 LINE       275
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT15,T16,T18
11CoveredT1,T2,T4

 LINE       276
 EXPRESSION (req_o & gnt_i)
             --1--   --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11CoveredT1,T2,T4

 LINE       287
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T4
1Not Covered

 LINE       304
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT13,T27,T44

 LINE       305
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------
-1--2-StatusTests
00Not Covered
01CoveredT13,T27,T44
10Not Covered

 LINE       315
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101CoveredT13,T27,T44
1110Not Covered
1111Not Covered

 LINE       315
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT13,T27,T44

 LINE       343
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       343
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       349
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       349
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------
-1--2-StatusTests
01CoveredT13,T27,T44
10Not Covered
11Not Covered

 LINE       349
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       361
 EXPRESSION (error_internal & tl_i_int.a_valid & ((~tl_o_int.a_ready)))
             -------1------   --------2-------   ----------3----------
-1--2--3-StatusTests
011CoveredT1,T2,T4
101CoveredT1,T2,T3
110CoveredT13,T27,T44
111CoveredT13,T27,T44

 LINE       371
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T4

 LINE       371
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT13,T27,T44
11CoveredT1,T2,T4

 LINE       371
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       371
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T4

 LINE       371
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T4

 LINE       371
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T4
11CoveredT13,T27,T44

 LINE       371
 EXPRESSION ((gnt_i | missed_err_gnt_q) & reqfifo_wready & sramreqfifo_wready & sramreqaddrfifo_wready)
             -------------1------------   -------2------   ---------3--------   -----------4----------
-1--2--3--4-StatusTests
0111Unreachable
1011CoveredT1,T2,T4
1101Not Covered
1110Unreachable
1111CoveredT1,T2,T3

 LINE       371
 SUB-EXPRESSION (gnt_i | missed_err_gnt_q)
                 --1--   --------2-------
-1--2-StatusTests
00UnreachableT1,T2,T4
01Unreachable
10CoveredT1,T2,T3

 LINE       392
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T4
110CoveredT13,T27,T44
111CoveredT1,T2,T4

 LINE       394
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT13,T27,T44
11CoveredT1,T2,T4

 LINE       395
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T4

 LINE       431
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT1,T2,T4

 LINE       431
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-
-1--2-StatusTests
01CoveredT1,T2,T4
10CoveredT13,T27,T44
11CoveredT1,T2,T4

 LINE       454
 EXPRESSION (((|wmask_intg)) & ((|wdata_intg)))
             -------1-------   -------2-------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T13
11CoveredT1,T2,T4

 LINE       462
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       462
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       476
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T4
11Not Covered

 LINE       479
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------
-1--2-StatusTests
01CoveredT1,T2,T4
10Unreachable
11Unreachable

 LINE       535
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       535
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT13,T27,T44
11Not Covered

 LINE       535
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT13,T27,T44

Cond Coverage for Module : tlul_adapter_sram ( parameter SramAw=7,SramDw=32,Outstanding=1,SramBusBankAW=12,ByteAccess=1,ErrOnWrite=1,ErrOnRead=0,CmdIntgCheck=0,EnableRspIntgGen=0,EnableDataIntgGen=0,EnableDataIntgPt=0,SecFifoPtr=0,EnableReadback=0,DataXorAddr=0,WidthMult=1,DataOutW=32,DataBitWidth=2,WoffsetWidth=1,DataWidth=32 )
Cond Coverage for Module self-instances :
SCORECOND
93.34 82.46
tb.dut.u_staterd.u_tlul_adapter

TotalCoveredPercent
Conditions1149482.46
Logical1149482.46
Non-Logical00
Event00

 LINE       114
 EXPRESSION (readback_error | readback_error_q)
             -------1------   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10Unreachable

 LINE       131
 EXPRESSION (intg_error || rsp_fifo_error || sramreqfifo_error || reqfifo_error)
             -----1----    -------2------    --------3--------    ------4------
-1--2--3--4-StatusTests
0000CoveredT1,T2,T3
0001Unreachable
0010Unreachable
0100Unreachable
1000Unreachable

 LINE       138
 EXPRESSION (intg_error | rsp_fifo_error | sramreqfifo_error | reqfifo_error | intg_error_q)
             -----1----   -------2------   --------3--------   ------4------   ------5-----
-1--2--3--4--5-StatusTests
00000CoveredT1,T2,T3
00001Not Covered
00010Unreachable
00100Unreachable
01000Unreachable
10000Unreachable

 LINE       144
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? (((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0)) : 1'b0)
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       144
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       144
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       144
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION (tl_i.a_opcode != Get)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       176
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----
-1--2--3--4--5--6-StatusTests
000000CoveredT1,T2,T4
000001Unreachable
000010CoveredT1,T2,T3
000100Not Covered
001000Unreachable
010000CoveredT13,T27,T44
100000Not Covered

 LINE       274
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT13,T27,T44
10CoveredT1,T2,T4
11CoveredT1,T2,T4

 LINE       275
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT15,T16,T18
11CoveredT1,T2,T4

 LINE       276
 EXPRESSION (req_o & gnt_i)
             --1--   --2--
-1--2-StatusTests
01Not Covered
10Not Covered
11CoveredT1,T2,T4

 LINE       287
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T4

 LINE       304
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT13,T27,T44
1CoveredT1,T2,T4

 LINE       305
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT13,T27,T44
10Not Covered

 LINE       315
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101CoveredT13,T27,T44
1110Not Covered
1111CoveredT1,T2,T4

 LINE       315
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T4

 LINE       343
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T4

 LINE       343
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T4

 LINE       349
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       349
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------
-1--2-StatusTests
01CoveredT13,T27,T44
10CoveredT1,T2,T4
11Not Covered

 LINE       349
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T4

 LINE       361
 EXPRESSION (error_internal & tl_i_int.a_valid & ((~tl_o_int.a_ready)))
             -------1------   --------2-------   ----------3----------
-1--2--3-StatusTests
011CoveredT1,T2,T4
101CoveredT1,T2,T3
110CoveredT13,T27,T44
111CoveredT13,T27,T44

 LINE       371
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT13,T27,T44

 LINE       371
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T4
11CoveredT13,T27,T44

 LINE       371
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       371
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T4

 LINE       371
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T4

 LINE       371
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T4
11CoveredT13,T27,T44

 LINE       371
 EXPRESSION ((gnt_i | missed_err_gnt_q) & reqfifo_wready & sramreqfifo_wready & sramreqaddrfifo_wready)
             -------------1------------   -------2------   ---------3--------   -----------4----------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011Not Covered
1101Not Covered
1110Unreachable
1111CoveredT1,T2,T4

 LINE       371
 SUB-EXPRESSION (gnt_i | missed_err_gnt_q)
                 --1--   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT13,T27,T44
10CoveredT1,T2,T4

 LINE       392
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T4
110CoveredT13,T27,T44
111CoveredT1,T2,T4

 LINE       394
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T4
11CoveredT13,T27,T44

 LINE       395
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T4

 LINE       431
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT13,T27,T44

 LINE       431
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-
-1--2-StatusTests
01CoveredT13,T27,T44
10CoveredT1,T2,T4
11CoveredT13,T27,T44

 LINE       454
 EXPRESSION (((|wmask_intg)) & ((|wdata_intg)))
             -------1-------   -------2-------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T13
11CoveredT1,T2,T4

 LINE       462
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       462
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       476
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T4

 LINE       479
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------
-1--2-StatusTests
01CoveredT13,T15,T18
10Not Covered
11CoveredT1,T2,T4

 LINE       535
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T4

 LINE       535
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT13,T27,T44
11CoveredT1,T2,T4

 LINE       535
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T4

Branch Coverage for Module : tlul_adapter_sram
Line No.TotalCoveredPercent
Branches 26 25 96.15
TERNARY 144 2 2 100.00
TERNARY 343 2 2 100.00
TERNARY 349 3 2 66.67
TERNARY 395 2 2 100.00
TERNARY 535 2 2 100.00
IF 129 2 2 100.00
IF 283 4 4 100.00
IF 303 3 3 100.00
IF 364 2 2 100.00
IF 428 2 2 100.00
IF 440 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 144 (((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 343 ((vld_rd_rsp & (~d_error))) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 349 ((vld_rd_rsp && reqfifo_rdata.error)) ? -2-: 349 (vld_rd_rsp) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Covered T1,T2,T4
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 395 (tl_i_int.a_valid) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 535 (((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 129 if ((!rst_ni)) -2-: 131 if ((((intg_error || rsp_fifo_error) || sramreqfifo_error) || reqfifo_error))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Unreachable
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 283 if (reqfifo_rvalid) -2-: 284 if (reqfifo_rdata.error) -3-: 287 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2--3-StatusTests
1 1 - Covered T13,T27,T44
1 0 1 Covered T1,T2,T4
1 0 0 Covered T1,T2,T4
0 - - Covered T1,T2,T3


LineNo. Expression -1-: 303 if (reqfifo_rvalid) -2-: 304 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2-StatusTests
1 1 Covered T1,T2,T4
1 0 Covered T1,T2,T4
0 - Covered T1,T2,T3


LineNo. Expression -1-: 364 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 428 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 440 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T3


Assert Coverage for Module : tlul_adapter_sram
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 13 13 100.00 13 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 13 13 100.00 13 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AddrOutKnown_A 2147483647 2147483647 0 0
DataIntgOptions_A 2060 2060 0 0
ReqOutKnown_A 2147483647 2147483647 0 0
SramDwHasByteGranularity_A 2060 2060 0 0
SramDwIsMultipleOfTlulWidth_A 2060 2060 0 0
TlOutKnownIfFifoKnown_A 2147483647 2147483647 0 0
TlOutValidKnown_A 2147483647 2147483647 0 0
WdataOutKnown_A 2147483647 2147483647 0 0
WeOutKnown_A 2147483647 2147483647 0 0
WmaskOutKnown_A 2147483647 2147483647 0 0
adapterNoReadOrWrite 2060 2060 0 0
rvalidHighReqFifoEmpty 2147483647 36683943 0 0
rvalidHighWhenRspFifoFull 2147483647 36683943 0 0


AddrOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 723804 723664 0 0
T2 33724 33574 0 0
T3 50932 50746 0 0
T4 7358 7104 0 0
T5 8424 8046 0 0
T13 668594 668570 0 0
T14 316894 316694 0 0
T15 45120 44974 0 0
T16 417400 417262 0 0
T17 84166 84032 0 0

DataIntgOptions_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2060 2060 0 0
T1 2 2 0 0
T2 2 2 0 0
T3 2 2 0 0
T4 2 2 0 0
T5 2 2 0 0
T13 2 2 0 0
T14 2 2 0 0
T15 2 2 0 0
T16 2 2 0 0
T17 2 2 0 0

ReqOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 723804 723664 0 0
T2 33724 33574 0 0
T3 50932 50746 0 0
T4 7358 7104 0 0
T5 8424 8046 0 0
T13 668594 668570 0 0
T14 316894 316694 0 0
T15 45120 44974 0 0
T16 417400 417262 0 0
T17 84166 84032 0 0

SramDwHasByteGranularity_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2060 2060 0 0
T1 2 2 0 0
T2 2 2 0 0
T3 2 2 0 0
T4 2 2 0 0
T5 2 2 0 0
T13 2 2 0 0
T14 2 2 0 0
T15 2 2 0 0
T16 2 2 0 0
T17 2 2 0 0

SramDwIsMultipleOfTlulWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2060 2060 0 0
T1 2 2 0 0
T2 2 2 0 0
T3 2 2 0 0
T4 2 2 0 0
T5 2 2 0 0
T13 2 2 0 0
T14 2 2 0 0
T15 2 2 0 0
T16 2 2 0 0
T17 2 2 0 0

TlOutKnownIfFifoKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 723804 723664 0 0
T2 33724 33574 0 0
T3 50932 50746 0 0
T4 7358 7104 0 0
T5 8424 8046 0 0
T13 668594 668570 0 0
T14 316894 316694 0 0
T15 45120 44974 0 0
T16 417400 417262 0 0
T17 84166 84032 0 0

TlOutValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 723804 723664 0 0
T2 33724 33574 0 0
T3 50932 50746 0 0
T4 7358 7104 0 0
T5 8424 8046 0 0
T13 668594 668570 0 0
T14 316894 316694 0 0
T15 45120 44974 0 0
T16 417400 417262 0 0
T17 84166 84032 0 0

WdataOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 723804 723664 0 0
T2 33724 33574 0 0
T3 50932 50746 0 0
T4 7358 7104 0 0
T5 8424 8046 0 0
T13 668594 668570 0 0
T14 316894 316694 0 0
T15 45120 44974 0 0
T16 417400 417262 0 0
T17 84166 84032 0 0

WeOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 723804 723664 0 0
T2 33724 33574 0 0
T3 50932 50746 0 0
T4 7358 7104 0 0
T5 8424 8046 0 0
T13 668594 668570 0 0
T14 316894 316694 0 0
T15 45120 44974 0 0
T16 417400 417262 0 0
T17 84166 84032 0 0

WmaskOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 723804 723664 0 0
T2 33724 33574 0 0
T3 50932 50746 0 0
T4 7358 7104 0 0
T5 8424 8046 0 0
T13 668594 668570 0 0
T14 316894 316694 0 0
T15 45120 44974 0 0
T16 417400 417262 0 0
T17 84166 84032 0 0

adapterNoReadOrWrite
NameAttemptsReal SuccessesFailuresIncomplete
Total 2060 2060 0 0
T1 2 2 0 0
T2 2 2 0 0
T3 2 2 0 0
T4 2 2 0 0
T5 2 2 0 0
T13 2 2 0 0
T14 2 2 0 0
T15 2 2 0 0
T16 2 2 0 0
T17 2 2 0 0

rvalidHighReqFifoEmpty
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 36683943 0 0
T1 361902 17918 0 0
T2 16862 546 0 0
T3 25466 0 0 0
T4 3679 68 0 0
T5 4212 52 0 0
T13 334297 25745 0 0
T14 158447 26340 0 0
T15 22560 546 0 0
T16 208700 6220 0 0
T17 42083 8482 0 0
T18 0 73459 0 0

rvalidHighWhenRspFifoFull
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 36683943 0 0
T1 361902 17918 0 0
T2 16862 546 0 0
T3 25466 0 0 0
T4 3679 68 0 0
T5 4212 52 0 0
T13 334297 25745 0 0
T14 158447 26340 0 0
T15 22560 546 0 0
T16 208700 6220 0 0
T17 42083 8482 0 0
T18 0 73459 0 0

Line Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo
Line No.TotalCoveredPercent
TOTAL686798.53
CONT_ASSIGN10700
CONT_ASSIGN11400
ALWAYS12933100.00
CONT_ASSIGN13811100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN16211100.00
CONT_ASSIGN17611100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN27411100.00
CONT_ASSIGN27511100.00
CONT_ASSIGN27611100.00
ALWAYS2818787.50
ALWAYS30166100.00
CONT_ASSIGN31511100.00
CONT_ASSIGN31911100.00
CONT_ASSIGN33811100.00
CONT_ASSIGN34311100.00
CONT_ASSIGN34911100.00
CONT_ASSIGN36111100.00
ALWAYS36433100.00
CONT_ASSIGN37111100.00
CONT_ASSIGN39211100.00
CONT_ASSIGN39311100.00
CONT_ASSIGN39411100.00
CONT_ASSIGN39511100.00
ALWAYS42566100.00
ALWAYS43755100.00
CONT_ASSIGN45211100.00
CONT_ASSIGN45311100.00
CONT_ASSIGN45411100.00
CONT_ASSIGN45811100.00
CONT_ASSIGN45911100.00
CONT_ASSIGN46111100.00
CONT_ASSIGN46211100.00
CONT_ASSIGN46911100.00
CONT_ASSIGN47211100.00
CONT_ASSIGN47611100.00
CONT_ASSIGN47700
CONT_ASSIGN47900
CONT_ASSIGN48111100.00
CONT_ASSIGN49000
ALWAYS52133100.00
CONT_ASSIGN52711100.00
CONT_ASSIGN53011100.00
CONT_ASSIGN53511100.00
CONT_ASSIGN54000
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
107 unreachable
114 unreachable
129 1 1
130 1 1
131 1 1
132 unreachable
MISSING_ELSE
138 1 1
144 1 1
151 1 1
162 1 1
176 1 1
188 1 1
274 1 1
275 1 1
276 1 1
281 1 1
283 1 1
284 1 1
286 1 1
287 1 1
288 0 1
291 1 1
294 1 1
301 1 1
303 1 1
304 1 1
305 1 1
307 1 1
310 1 1
315 1 1
319 1 1
338 1 1
343 1 1
349 1 1
361 1 1
364 1 1
365 1 1
367 1 1
371 1 1
392 1 1
393 1 1
394 1 1
395 1 1
425 1 1
426 1 1
428 1 1
429 1 1
430 1 1
431 1 1
MISSING_ELSE
437 1 1
438 1 1
440 1 1
441 1 1
442 1 1
MISSING_ELSE
452 1 1
453 1 1
454 1 1
458 1 1
459 1 1
461 1 1
462 1 1
469 1 1
472 1 1
476 1 1
477 unreachable
479 unreachable
481 1 1
490 unreachable
521 1 1
522 1 1
523 1 1
527 1 1
530 1 1
535 1 1
540 unreachable


Cond Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo
TotalCoveredPercent
Conditions1088477.78
Logical1088477.78
Non-Logical00
Event00

 LINE       114
 EXPRESSION (readback_error | readback_error_q)
             -------1------   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10Unreachable

 LINE       131
 EXPRESSION (intg_error || rsp_fifo_error || sramreqfifo_error || reqfifo_error)
             -----1----    -------2------    --------3--------    ------4------
-1--2--3--4-StatusTests
0000CoveredT1,T2,T3
0001Unreachable
0010Unreachable
0100Unreachable
1000Unreachable

 LINE       138
 EXPRESSION (intg_error | rsp_fifo_error | sramreqfifo_error | reqfifo_error | intg_error_q)
             -----1----   -------2------   --------3--------   ------4------   ------5-----
-1--2--3--4--5-StatusTests
00000CoveredT1,T2,T3
00001Not Covered
00010Unreachable
00100Unreachable
01000Unreachable
10000Unreachable

 LINE       144
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? (((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0)) : 1'b0)
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       144
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       144
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       144
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       162
 EXPRESSION (tl_i.a_opcode == Get)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       176
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----
-1--2--3--4--5--6-StatusTests
000000CoveredT1,T2,T4
000001Unreachable
000010CoveredT1,T2,T3
000100Not Covered
001000CoveredT13,T27,T44
010000Unreachable
100000Not Covered

 LINE       274
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T4
11CoveredT1,T2,T4

 LINE       275
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT15,T16,T18
11CoveredT1,T2,T4

 LINE       276
 EXPRESSION (req_o & gnt_i)
             --1--   --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11CoveredT1,T2,T4

 LINE       287
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T4
1Not Covered

 LINE       304
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT13,T27,T44

 LINE       305
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------
-1--2-StatusTests
00Not Covered
01CoveredT13,T27,T44
10Not Covered

 LINE       315
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101CoveredT13,T27,T44
1110Not Covered
1111Not Covered

 LINE       315
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT13,T27,T44

 LINE       343
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       343
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       349
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       349
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------
-1--2-StatusTests
01CoveredT13,T27,T44
10Not Covered
11Not Covered

 LINE       349
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       361
 EXPRESSION (error_internal & tl_i_int.a_valid & ((~tl_o_int.a_ready)))
             -------1------   --------2-------   ----------3----------
-1--2--3-StatusTests
011CoveredT1,T2,T4
101CoveredT1,T2,T3
110CoveredT13,T27,T44
111CoveredT13,T27,T44

 LINE       371
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T4

 LINE       371
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT13,T27,T44
11CoveredT1,T2,T4

 LINE       371
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       371
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T4

 LINE       371
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T4

 LINE       371
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T4
11CoveredT13,T27,T44

 LINE       371
 EXPRESSION ((gnt_i | missed_err_gnt_q) & reqfifo_wready & sramreqfifo_wready & sramreqaddrfifo_wready)
             -------------1------------   -------2------   ---------3--------   -----------4----------
-1--2--3--4-StatusTests
0111Unreachable
1011CoveredT1,T2,T4
1101Not Covered
1110Unreachable
1111CoveredT1,T2,T3

 LINE       371
 SUB-EXPRESSION (gnt_i | missed_err_gnt_q)
                 --1--   --------2-------
-1--2-StatusTests
00UnreachableT1,T2,T4
01Unreachable
10CoveredT1,T2,T3

 LINE       392
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T4
110CoveredT13,T27,T44
111CoveredT1,T2,T4

 LINE       394
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT13,T27,T44
11CoveredT1,T2,T4

 LINE       395
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T4

 LINE       431
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT1,T2,T4

 LINE       431
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-
-1--2-StatusTests
01CoveredT1,T2,T4
10CoveredT13,T27,T44
11CoveredT1,T2,T4

 LINE       454
 EXPRESSION (((|wmask_intg)) & ((|wdata_intg)))
             -------1-------   -------2-------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T13
11CoveredT1,T2,T4

 LINE       462
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       462
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       476
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T4
11Not Covered

 LINE       479
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------
-1--2-StatusTests
01CoveredT1,T2,T4
10Unreachable
11Unreachable

 LINE       535
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       535
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT13,T27,T44
11Not Covered

 LINE       535
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT13,T27,T44

Branch Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo
Line No.TotalCoveredPercent
Branches 26 21 80.77
TERNARY 144 2 2 100.00
TERNARY 343 2 1 50.00
TERNARY 349 3 1 33.33
TERNARY 395 2 2 100.00
TERNARY 535 2 1 50.00
IF 129 2 2 100.00
IF 283 4 3 75.00
IF 303 3 3 100.00
IF 364 2 2 100.00
IF 428 2 2 100.00
IF 440 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 144 (((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 343 ((vld_rd_rsp & (~d_error))) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 349 ((vld_rd_rsp && reqfifo_rdata.error)) ? -2-: 349 (vld_rd_rsp) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Not Covered
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 395 (tl_i_int.a_valid) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 535 (((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 129 if ((!rst_ni)) -2-: 131 if ((((intg_error || rsp_fifo_error) || sramreqfifo_error) || reqfifo_error))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Unreachable
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 283 if (reqfifo_rvalid) -2-: 284 if (reqfifo_rdata.error) -3-: 287 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2--3-StatusTests
1 1 - Covered T13,T27,T44
1 0 1 Not Covered
1 0 0 Covered T1,T2,T4
0 - - Covered T1,T2,T3


LineNo. Expression -1-: 303 if (reqfifo_rvalid) -2-: 304 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2-StatusTests
1 1 Covered T13,T27,T44
1 0 Covered T1,T2,T4
0 - Covered T1,T2,T3


LineNo. Expression -1-: 364 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 428 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 440 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 13 13 100.00 11 84.62
Cover properties 0 0 0
Cover sequences 0 0 0
Total 13 13 100.00 11 84.62




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AddrOutKnown_A 2147483647 2147483647 0 0
DataIntgOptions_A 1030 1030 0 0
ReqOutKnown_A 2147483647 2147483647 0 0
SramDwHasByteGranularity_A 1030 1030 0 0
SramDwIsMultipleOfTlulWidth_A 1030 1030 0 0
TlOutKnownIfFifoKnown_A 2147483647 2147483647 0 0
TlOutValidKnown_A 2147483647 2147483647 0 0
WdataOutKnown_A 2147483647 2147483647 0 0
WeOutKnown_A 2147483647 2147483647 0 0
WmaskOutKnown_A 2147483647 2147483647 0 0
adapterNoReadOrWrite 1030 1030 0 0
rvalidHighReqFifoEmpty 2147483647 0 0 0
rvalidHighWhenRspFifoFull 2147483647 0 0 0


AddrOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 361902 361832 0 0
T2 16862 16787 0 0
T3 25466 25373 0 0
T4 3679 3552 0 0
T5 4212 4023 0 0
T13 334297 334285 0 0
T14 158447 158347 0 0
T15 22560 22487 0 0
T16 208700 208631 0 0
T17 42083 42016 0 0

DataIntgOptions_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1030 1030 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

ReqOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 361902 361832 0 0
T2 16862 16787 0 0
T3 25466 25373 0 0
T4 3679 3552 0 0
T5 4212 4023 0 0
T13 334297 334285 0 0
T14 158447 158347 0 0
T15 22560 22487 0 0
T16 208700 208631 0 0
T17 42083 42016 0 0

SramDwHasByteGranularity_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1030 1030 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

SramDwIsMultipleOfTlulWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1030 1030 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

TlOutKnownIfFifoKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 361902 361832 0 0
T2 16862 16787 0 0
T3 25466 25373 0 0
T4 3679 3552 0 0
T5 4212 4023 0 0
T13 334297 334285 0 0
T14 158447 158347 0 0
T15 22560 22487 0 0
T16 208700 208631 0 0
T17 42083 42016 0 0

TlOutValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 361902 361832 0 0
T2 16862 16787 0 0
T3 25466 25373 0 0
T4 3679 3552 0 0
T5 4212 4023 0 0
T13 334297 334285 0 0
T14 158447 158347 0 0
T15 22560 22487 0 0
T16 208700 208631 0 0
T17 42083 42016 0 0

WdataOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 361902 361832 0 0
T2 16862 16787 0 0
T3 25466 25373 0 0
T4 3679 3552 0 0
T5 4212 4023 0 0
T13 334297 334285 0 0
T14 158447 158347 0 0
T15 22560 22487 0 0
T16 208700 208631 0 0
T17 42083 42016 0 0

WeOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 361902 361832 0 0
T2 16862 16787 0 0
T3 25466 25373 0 0
T4 3679 3552 0 0
T5 4212 4023 0 0
T13 334297 334285 0 0
T14 158447 158347 0 0
T15 22560 22487 0 0
T16 208700 208631 0 0
T17 42083 42016 0 0

WmaskOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 361902 361832 0 0
T2 16862 16787 0 0
T3 25466 25373 0 0
T4 3679 3552 0 0
T5 4212 4023 0 0
T13 334297 334285 0 0
T14 158447 158347 0 0
T15 22560 22487 0 0
T16 208700 208631 0 0
T17 42083 42016 0 0

adapterNoReadOrWrite
NameAttemptsReal SuccessesFailuresIncomplete
Total 1030 1030 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

rvalidHighReqFifoEmpty
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 0 0 0

rvalidHighWhenRspFifoFull
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 0 0 0

Line Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter
Line No.TotalCoveredPercent
TOTAL717098.59
CONT_ASSIGN10700
CONT_ASSIGN11400
ALWAYS12933100.00
CONT_ASSIGN13811100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN17611100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN27411100.00
CONT_ASSIGN27511100.00
CONT_ASSIGN27611100.00
ALWAYS2818787.50
ALWAYS30166100.00
CONT_ASSIGN31511100.00
CONT_ASSIGN31911100.00
CONT_ASSIGN33811100.00
CONT_ASSIGN34311100.00
CONT_ASSIGN34911100.00
CONT_ASSIGN36111100.00
ALWAYS36433100.00
CONT_ASSIGN37111100.00
CONT_ASSIGN39211100.00
CONT_ASSIGN39311100.00
CONT_ASSIGN39411100.00
CONT_ASSIGN39511100.00
ALWAYS42566100.00
ALWAYS43755100.00
CONT_ASSIGN45211100.00
CONT_ASSIGN45311100.00
CONT_ASSIGN45411100.00
CONT_ASSIGN45811100.00
CONT_ASSIGN45911100.00
CONT_ASSIGN46111100.00
CONT_ASSIGN46211100.00
CONT_ASSIGN46911100.00
CONT_ASSIGN47211100.00
CONT_ASSIGN47611100.00
CONT_ASSIGN47711100.00
CONT_ASSIGN47911100.00
CONT_ASSIGN48111100.00
CONT_ASSIGN49011100.00
ALWAYS52133100.00
CONT_ASSIGN52711100.00
CONT_ASSIGN53011100.00
CONT_ASSIGN53511100.00
CONT_ASSIGN54000
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
107 unreachable
114 unreachable
129 1 1
130 1 1
131 1 1
132 unreachable
MISSING_ELSE
138 1 1
144 1 1
151 1 1
156 1 1
176 1 1
188 1 1
274 1 1
275 1 1
276 1 1
281 1 1
283 1 1
284 1 1
286 1 1
287 1 1
288 1 1
291 0 1
294 1 1
301 1 1
303 1 1
304 1 1
305 1 1
307 1 1
310 1 1
315 1 1
319 1 1
338 1 1
343 1 1
349 1 1
361 1 1
364 1 1
365 1 1
367 1 1
371 1 1
392 1 1
393 1 1
394 1 1
395 1 1
425 1 1
426 1 1
428 1 1
429 1 1
430 1 1
431 1 1
MISSING_ELSE
437 1 1
438 1 1
440 1 1
441 1 1
442 1 1
MISSING_ELSE
452 1 1
453 1 1
454 1 1
458 1 1
459 1 1
461 1 1
462 1 1
469 1 1
472 1 1
476 1 1
477 1 1
479 1 1
481 1 1
490 1 1
521 1 1
522 1 1
523 1 1
527 1 1
530 1 1
535 1 1
540 unreachable


Cond Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter
TotalCoveredPercent
Conditions1149482.46
Logical1149482.46
Non-Logical00
Event00

 LINE       114
 EXPRESSION (readback_error | readback_error_q)
             -------1------   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10Unreachable

 LINE       131
 EXPRESSION (intg_error || rsp_fifo_error || sramreqfifo_error || reqfifo_error)
             -----1----    -------2------    --------3--------    ------4------
-1--2--3--4-StatusTests
0000CoveredT1,T2,T3
0001Unreachable
0010Unreachable
0100Unreachable
1000Unreachable

 LINE       138
 EXPRESSION (intg_error | rsp_fifo_error | sramreqfifo_error | reqfifo_error | intg_error_q)
             -----1----   -------2------   --------3--------   ------4------   ------5-----
-1--2--3--4--5-StatusTests
00000CoveredT1,T2,T3
00001Not Covered
00010Unreachable
00100Unreachable
01000Unreachable
10000Unreachable

 LINE       144
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? (((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0)) : 1'b0)
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       144
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       144
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       144
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION (tl_i.a_opcode != Get)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       176
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----
-1--2--3--4--5--6-StatusTests
000000CoveredT1,T2,T4
000001Unreachable
000010CoveredT1,T2,T3
000100Not Covered
001000Unreachable
010000CoveredT13,T27,T44
100000Not Covered

 LINE       274
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT13,T27,T44
10CoveredT1,T2,T4
11CoveredT1,T2,T4

 LINE       275
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT15,T16,T18
11CoveredT1,T2,T4

 LINE       276
 EXPRESSION (req_o & gnt_i)
             --1--   --2--
-1--2-StatusTests
01Not Covered
10Not Covered
11CoveredT1,T2,T4

 LINE       287
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T4

 LINE       304
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT13,T27,T44
1CoveredT1,T2,T4

 LINE       305
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT13,T27,T44
10Not Covered

 LINE       315
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101CoveredT13,T27,T44
1110Not Covered
1111CoveredT1,T2,T4

 LINE       315
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T4

 LINE       343
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T4

 LINE       343
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T4

 LINE       349
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       349
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------
-1--2-StatusTests
01CoveredT13,T27,T44
10CoveredT1,T2,T4
11Not Covered

 LINE       349
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T4

 LINE       361
 EXPRESSION (error_internal & tl_i_int.a_valid & ((~tl_o_int.a_ready)))
             -------1------   --------2-------   ----------3----------
-1--2--3-StatusTests
011CoveredT1,T2,T4
101CoveredT1,T2,T3
110CoveredT13,T27,T44
111CoveredT13,T27,T44

 LINE       371
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT13,T27,T44

 LINE       371
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T4
11CoveredT13,T27,T44

 LINE       371
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       371
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T4

 LINE       371
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T4

 LINE       371
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T4
11CoveredT13,T27,T44

 LINE       371
 EXPRESSION ((gnt_i | missed_err_gnt_q) & reqfifo_wready & sramreqfifo_wready & sramreqaddrfifo_wready)
             -------------1------------   -------2------   ---------3--------   -----------4----------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011Not Covered
1101Not Covered
1110Unreachable
1111CoveredT1,T2,T4

 LINE       371
 SUB-EXPRESSION (gnt_i | missed_err_gnt_q)
                 --1--   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT13,T27,T44
10CoveredT1,T2,T4

 LINE       392
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T4
110CoveredT13,T27,T44
111CoveredT1,T2,T4

 LINE       394
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T4
11CoveredT13,T27,T44

 LINE       395
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T4

 LINE       431
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT13,T27,T44

 LINE       431
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-
-1--2-StatusTests
01CoveredT13,T27,T44
10CoveredT1,T2,T4
11CoveredT13,T27,T44

 LINE       454
 EXPRESSION (((|wmask_intg)) & ((|wdata_intg)))
             -------1-------   -------2-------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T13
11CoveredT1,T2,T4

 LINE       462
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       462
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       476
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T4

 LINE       479
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------
-1--2-StatusTests
01CoveredT13,T15,T18
10Not Covered
11CoveredT1,T2,T4

 LINE       535
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T4

 LINE       535
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT13,T27,T44
11CoveredT1,T2,T4

 LINE       535
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T4

Branch Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter
Line No.TotalCoveredPercent
Branches 26 24 92.31
TERNARY 144 2 2 100.00
TERNARY 343 2 2 100.00
TERNARY 349 3 2 66.67
TERNARY 395 2 2 100.00
TERNARY 535 2 2 100.00
IF 129 2 2 100.00
IF 283 4 3 75.00
IF 303 3 3 100.00
IF 364 2 2 100.00
IF 428 2 2 100.00
IF 440 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 144 (((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 343 ((vld_rd_rsp & (~d_error))) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 349 ((vld_rd_rsp && reqfifo_rdata.error)) ? -2-: 349 (vld_rd_rsp) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Covered T1,T2,T4
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 395 (tl_i_int.a_valid) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 535 (((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 129 if ((!rst_ni)) -2-: 131 if ((((intg_error || rsp_fifo_error) || sramreqfifo_error) || reqfifo_error))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Unreachable
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 283 if (reqfifo_rvalid) -2-: 284 if (reqfifo_rdata.error) -3-: 287 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2--3-StatusTests
1 1 - Covered T13,T27,T44
1 0 1 Covered T1,T2,T4
1 0 0 Not Covered
0 - - Covered T1,T2,T3


LineNo. Expression -1-: 303 if (reqfifo_rvalid) -2-: 304 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2-StatusTests
1 1 Covered T1,T2,T4
1 0 Covered T13,T27,T44
0 - Covered T1,T2,T3


LineNo. Expression -1-: 364 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 428 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 440 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 13 13 100.00 13 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 13 13 100.00 13 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AddrOutKnown_A 2147483647 2147483647 0 0
DataIntgOptions_A 1030 1030 0 0
ReqOutKnown_A 2147483647 2147483647 0 0
SramDwHasByteGranularity_A 1030 1030 0 0
SramDwIsMultipleOfTlulWidth_A 1030 1030 0 0
TlOutKnownIfFifoKnown_A 2147483647 2147483647 0 0
TlOutValidKnown_A 2147483647 2147483647 0 0
WdataOutKnown_A 2147483647 2147483647 0 0
WeOutKnown_A 2147483647 2147483647 0 0
WmaskOutKnown_A 2147483647 2147483647 0 0
adapterNoReadOrWrite 1030 1030 0 0
rvalidHighReqFifoEmpty 2147483647 36683943 0 0
rvalidHighWhenRspFifoFull 2147483647 36683943 0 0


AddrOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 361902 361832 0 0
T2 16862 16787 0 0
T3 25466 25373 0 0
T4 3679 3552 0 0
T5 4212 4023 0 0
T13 334297 334285 0 0
T14 158447 158347 0 0
T15 22560 22487 0 0
T16 208700 208631 0 0
T17 42083 42016 0 0

DataIntgOptions_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1030 1030 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

ReqOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 361902 361832 0 0
T2 16862 16787 0 0
T3 25466 25373 0 0
T4 3679 3552 0 0
T5 4212 4023 0 0
T13 334297 334285 0 0
T14 158447 158347 0 0
T15 22560 22487 0 0
T16 208700 208631 0 0
T17 42083 42016 0 0

SramDwHasByteGranularity_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1030 1030 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

SramDwIsMultipleOfTlulWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1030 1030 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

TlOutKnownIfFifoKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 361902 361832 0 0
T2 16862 16787 0 0
T3 25466 25373 0 0
T4 3679 3552 0 0
T5 4212 4023 0 0
T13 334297 334285 0 0
T14 158447 158347 0 0
T15 22560 22487 0 0
T16 208700 208631 0 0
T17 42083 42016 0 0

TlOutValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 361902 361832 0 0
T2 16862 16787 0 0
T3 25466 25373 0 0
T4 3679 3552 0 0
T5 4212 4023 0 0
T13 334297 334285 0 0
T14 158447 158347 0 0
T15 22560 22487 0 0
T16 208700 208631 0 0
T17 42083 42016 0 0

WdataOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 361902 361832 0 0
T2 16862 16787 0 0
T3 25466 25373 0 0
T4 3679 3552 0 0
T5 4212 4023 0 0
T13 334297 334285 0 0
T14 158447 158347 0 0
T15 22560 22487 0 0
T16 208700 208631 0 0
T17 42083 42016 0 0

WeOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 361902 361832 0 0
T2 16862 16787 0 0
T3 25466 25373 0 0
T4 3679 3552 0 0
T5 4212 4023 0 0
T13 334297 334285 0 0
T14 158447 158347 0 0
T15 22560 22487 0 0
T16 208700 208631 0 0
T17 42083 42016 0 0

WmaskOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 361902 361832 0 0
T2 16862 16787 0 0
T3 25466 25373 0 0
T4 3679 3552 0 0
T5 4212 4023 0 0
T13 334297 334285 0 0
T14 158447 158347 0 0
T15 22560 22487 0 0
T16 208700 208631 0 0
T17 42083 42016 0 0

adapterNoReadOrWrite
NameAttemptsReal SuccessesFailuresIncomplete
Total 1030 1030 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

rvalidHighReqFifoEmpty
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 36683943 0 0
T1 361902 17918 0 0
T2 16862 546 0 0
T3 25466 0 0 0
T4 3679 68 0 0
T5 4212 52 0 0
T13 334297 25745 0 0
T14 158447 26340 0 0
T15 22560 546 0 0
T16 208700 6220 0 0
T17 42083 8482 0 0
T18 0 73459 0 0

rvalidHighWhenRspFifoFull
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 36683943 0 0
T1 361902 17918 0 0
T2 16862 546 0 0
T3 25466 0 0 0
T4 3679 68 0 0
T5 4212 52 0 0
T13 334297 25745 0 0
T14 158447 26340 0 0
T15 22560 546 0 0
T16 208700 6220 0 0
T17 42083 8482 0 0
T18 0 73459 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%