Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	256187250	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

202214785

1

T1

888339

T2

1418

T3

1454

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	241621600	1			T1	110683		T2	1069		T3	1177
values[0x0]	104111230	1			T1	448648		T2	460		T3	549
values[0x1]	112669205	1			T1	486961		T2	515		T3	544

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	199615214	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

258786821

1

T1

114061

T2

1559

T3

1662

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1369437	1			T1	8210		T3	14		T13	11
valid_sources[0x01]	1372490	1			T1	8181		T3	8		T13	10
valid_sources[0x02]	1356568	1			T1	7807		T3	4		T13	3
valid_sources[0x03]	1834762	1			T1	7988		T3	8		T13	3
valid_sources[0x04]	1361149	1			T1	7874		T3	9		T13	9
valid_sources[0x05]	1367046	1			T1	8068		T3	10		T20	1
valid_sources[0x06]	1363799	1			T1	8113		T3	12		T13	19
valid_sources[0x07]	1360038	1			T1	7804		T3	13		T13	3
valid_sources[0x08]	1359765	1			T1	7873		T3	6		T13	2
valid_sources[0x09]	1369054	1			T1	8239		T3	10		T13	4
valid_sources[0x0a]	1359620	1			T1	7565		T3	5		T13	6
valid_sources[0x0b]	1368293	1			T1	7748		T3	11		T13	6
valid_sources[0x0c]	1360837	1			T1	7836		T3	11		T13	3
valid_sources[0x0d]	1998510	1			T1	7802		T3	10		T13	8
valid_sources[0x0e]	1367248	1			T1	8176		T3	10		T13	4
valid_sources[0x0f]	1818370	1			T1	7847		T3	5		T20	8
valid_sources[0x10]	1358571	1			T1	8186		T3	5		T13	19
valid_sources[0x11]	1362748	1			T1	7812		T3	10		T13	10
valid_sources[0x12]	1757827	1			T1	7742		T3	7		T13	8
valid_sources[0x13]	2283433	1			T1	7560		T3	8		T13	5
valid_sources[0x14]	1363301	1			T1	8108		T3	3		T13	9
valid_sources[0x15]	3809631	1			T1	7668		T3	10		T13	7
valid_sources[0x16]	1364977	1			T1	8093		T3	8		T13	6
valid_sources[0x17]	1493008	1			T1	7875		T3	9		T13	11
valid_sources[0x18]	1363690	1			T1	7664		T3	12		T13	9
valid_sources[0x19]	1367763	1			T1	8264		T3	7		T13	10
valid_sources[0x1a]	1833312	1			T1	7893		T3	7		T13	14
valid_sources[0x1b]	1360752	1			T1	8306		T3	11		T13	6
valid_sources[0x1c]	1359104	1			T1	8082		T3	11		T13	7
valid_sources[0x1d]	3405696	1			T1	8162		T3	7		T13	2
valid_sources[0x1e]	1376293	1			T1	7775		T3	12		T13	5
valid_sources[0x1f]	1355537	1			T1	8014		T3	4		T13	5
valid_sources[0x20]	2261307	1			T1	7667		T3	9		T13	2
valid_sources[0x21]	2046425	1			T1	7881		T3	5		T13	7
valid_sources[0x22]	1508342	1			T1	7991		T3	12		T13	5
valid_sources[0x23]	2271515	1			T1	8336		T3	12		T13	6
valid_sources[0x24]	1366639	1			T1	7745		T3	4		T13	5
valid_sources[0x25]	1367891	1			T1	7959		T3	7		T13	7
valid_sources[0x26]	1511473	1			T1	8046		T3	7		T13	15
valid_sources[0x27]	1356422	1			T1	7922		T3	9		T20	2
valid_sources[0x28]	2228193	1			T1	7729		T3	10		T13	10
valid_sources[0x29]	1846049	1			T1	8347		T3	4		T13	5
valid_sources[0x2a]	1359301	1			T1	7893		T3	4		T13	2
valid_sources[0x2b]	1396903	1			T1	7699		T3	5		T13	10
valid_sources[0x2c]	1353785	1			T1	7537		T3	14		T13	5
valid_sources[0x2d]	1370364	1			T1	7578		T3	10		T13	21
valid_sources[0x2e]	1362778	1			T1	7876		T3	8		T13	16
valid_sources[0x2f]	3769486	1			T1	8068		T3	5		T13	2
valid_sources[0x30]	3891754	1			T1	7963		T3	9		T13	7
valid_sources[0x31]	1368065	1			T1	8245		T3	10		T20	1
valid_sources[0x32]	1398073	1			T1	8237		T3	5		T13	8
valid_sources[0x33]	1463615	1			T1	7984		T3	8		T13	2
valid_sources[0x34]	2264474	1			T1	7783		T3	13		T13	6
valid_sources[0x35]	1367492	1			T1	8066		T3	8		T13	8
valid_sources[0x36]	1361493	1			T1	7856		T3	6		T13	4
valid_sources[0x37]	1383721	1			T1	8085		T3	4		T13	7
valid_sources[0x38]	2281483	1			T1	7821		T3	15		T13	7
valid_sources[0x39]	1371811	1			T1	8411		T3	11		T13	8
valid_sources[0x3a]	2286356	1			T1	8248		T3	7		T20	2
valid_sources[0x3b]	3409959	1			T1	7913		T3	4		T13	16
valid_sources[0x3c]	1409265	1			T1	8391		T3	12		T13	8
valid_sources[0x3d]	2360212	1			T1	7721		T3	13		T13	4
valid_sources[0x3e]	1376215	1			T1	8266		T3	7		T13	8
valid_sources[0x3f]	3399545	1			T1	8326		T3	5		T13	5
valid_sources[0x40]	2258316	1			T1	7988		T3	6		T13	9
valid_sources[0x41]	3963433	1			T1	7718		T3	9		T13	9
valid_sources[0x42]	3653110	1			T1	7871		T3	7		T13	4
valid_sources[0x43]	3734272	1			T1	8199		T3	8		T13	11
valid_sources[0x44]	1638505	1			T1	8203		T2	2044		T3	6
valid_sources[0x45]	1360909	1			T1	8119		T3	9		T13	3
valid_sources[0x46]	1392832	1			T1	8446		T3	10		T13	8
valid_sources[0x47]	1358398	1			T1	8315		T3	5		T13	6
valid_sources[0x48]	1364946	1			T1	8068		T3	8		T13	3
valid_sources[0x49]	1364371	1			T1	8053		T3	9		T13	3
valid_sources[0x4a]	2032463	1			T1	7938		T3	12		T13	11
valid_sources[0x4b]	1414675	1			T1	8086		T3	4		T13	11
valid_sources[0x4c]	1355604	1			T1	8264		T3	7		T13	5
valid_sources[0x4d]	1455596	1			T1	7814		T3	14		T13	10
valid_sources[0x4e]	1359712	1			T1	7934		T3	14		T13	9
valid_sources[0x4f]	1363387	1			T1	7847		T3	5		T13	11
valid_sources[0x50]	3828910	1			T1	8047		T3	3		T13	4
valid_sources[0x51]	1359875	1			T1	7800		T3	6		T13	6
valid_sources[0x52]	4273543	1			T1	7744		T3	5		T13	5
valid_sources[0x53]	2270907	1			T1	7948		T3	4		T13	6
valid_sources[0x54]	1362504	1			T1	8243		T3	8		T13	4
valid_sources[0x55]	1397747	1			T1	8027		T3	9		T13	6
valid_sources[0x56]	1366702	1			T1	7955		T3	6		T13	9
valid_sources[0x57]	1369023	1			T1	7601		T3	11		T13	12
valid_sources[0x58]	1364925	1			T1	7844		T3	10		T13	8
valid_sources[0x59]	1359283	1			T1	7894		T3	13		T13	7
valid_sources[0x5a]	1370513	1			T1	7840		T3	13		T13	3
valid_sources[0x5b]	2036441	1			T1	7907		T3	13		T13	8
valid_sources[0x5c]	5864546	1			T1	7720		T3	8		T13	7
valid_sources[0x5d]	1361966	1			T1	8154		T3	6		T13	7
valid_sources[0x5e]	1379353	1			T1	8255		T3	9		T13	3
valid_sources[0x5f]	2455876	1			T1	8262		T3	8		T13	5
valid_sources[0x60]	1415181	1			T1	7670		T3	6		T13	11
valid_sources[0x61]	1365345	1			T1	8033		T3	8		T13	7
valid_sources[0x62]	2035798	1			T1	8050		T3	15		T13	12
valid_sources[0x63]	1363863	1			T1	8276		T3	8		T13	7
valid_sources[0x64]	1383830	1			T1	8102		T3	7		T13	7
valid_sources[0x65]	4930422	1			T1	8228		T3	9		T13	14
valid_sources[0x66]	1359276	1			T1	7981		T3	13		T13	5
valid_sources[0x67]	2244972	1			T1	7829		T3	10		T13	7
valid_sources[0x68]	1463026	1			T1	7934		T3	9		T13	7
valid_sources[0x69]	1387150	1			T1	8011		T3	11		T13	6
valid_sources[0x6a]	2016353	1			T1	7778		T3	13		T20	3
valid_sources[0x6b]	1819531	1			T1	7856		T3	16		T13	8
valid_sources[0x6c]	1360438	1			T1	8088		T3	8		T13	12
valid_sources[0x6d]	1355620	1			T1	8068		T3	3		T13	6
valid_sources[0x6e]	1812390	1			T1	7947		T3	13		T13	11
valid_sources[0x6f]	1364004	1			T1	8023		T3	9		T13	9
valid_sources[0x70]	1363240	1			T1	7690		T3	9		T13	14
valid_sources[0x71]	1490295	1			T1	7686		T3	7		T13	5
valid_sources[0x72]	1366686	1			T1	8345		T3	13		T13	19
valid_sources[0x73]	3802232	1			T1	7967		T3	8		T13	11
valid_sources[0x74]	1383685	1			T1	7561		T3	7		T13	8
valid_sources[0x75]	2371606	1			T1	8049		T3	6		T13	3
valid_sources[0x76]	2257685	1			T1	7947		T3	9		T20	3
valid_sources[0x77]	1365795	1			T1	7717		T3	10		T13	4
valid_sources[0x78]	2078427	1			T1	7940		T3	8		T13	11
valid_sources[0x79]	1367180	1			T1	7752		T3	14		T13	11
valid_sources[0x7a]	2036776	1			T1	8220		T3	7		T13	20
valid_sources[0x7b]	3768352	1			T1	7764		T3	10		T13	12
valid_sources[0x7c]	3722728	1			T1	8265		T3	6		T13	14
valid_sources[0x7d]	1359201	1			T1	8082		T3	12		T13	11
valid_sources[0x7e]	1365518	1			T1	7845		T3	10		T13	4
valid_sources[0x7f]	1366447	1			T1	7971		T3	9		T13	11
valid_sources[0x80]	1782966	1			T1	8015		T3	7		T13	15

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

88016529

1

T1

419358

T2

693

T3

721

values[0x0]

all_enables

biggest_size

61413721

1

T1

253800

T2

351

T3

396

values[0x1]

all_enables

biggest_size

52784535

1

T1

215181

T2

374

T3

337