Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

259404094

1

T1

115410

T2

626

T3

816

full_word

202418219

1

T1

888339

T2

1418

T3

1454

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	461822003	1			T1	204244		T2	2044		T3	2270
auto[TlIntgErrCmd]	116	1			T121	5		T122	1		T123	10
auto[TlIntgErrData]	93	1			T121	3		T122	4		T123	3
auto[TlIntgErrBoth]	101	1			T121	2		T122	5		T123	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

242248969

1

T1

110683

T2

1069

T3

1177

auto[1]

219573344

1

T1

935609

T2

975

T3

1093

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	154181077	1			T1	687473		T2	376		T3	456
auto[TlIntgErrNone]	partial	auto[1]	105222731	1			T1	466628		T2	250		T3	360
auto[TlIntgErrNone]	full_word	auto[0]	88067754	1			T1	419358		T2	693		T3	721
auto[TlIntgErrNone]	full_word	auto[1]	114350441	1			T1	468981		T2	725		T3	733
auto[TlIntgErrCmd]	partial	auto[0]	49	1			T121	1		T123	3		T127	2
auto[TlIntgErrCmd]	partial	auto[1]	61	1			T121	4		T122	1		T123	6
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T123	1		T187	2		T184	1
auto[TlIntgErrCmd]	full_word	auto[1]	1	1			T188	1		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	39	1			T122	2		T123	1		T127	1
auto[TlIntgErrData]	partial	auto[1]	48	1			T121	3		T122	2		T123	2
auto[TlIntgErrData]	full_word	auto[0]	3	1			T189	1		T190	1		T191	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T189	1		T192	1		T193	1
auto[TlIntgErrBoth]	partial	auto[0]	37	1			T121	1		T122	2		T123	2
auto[TlIntgErrBoth]	partial	auto[1]	52	1			T121	1		T122	2		T123	3
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T122	1		T123	1		T186	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T123	1		T189	1		T194	1